Capacitor With Side Silicon Portions For Miniaturization
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Solution Overview
Problem
The challenge is to develop a capacitor with high electrostatic capacitance that is suitable for miniaturization, as existing capacitors with porous metal sintered bodies and dielectric layers increase in size due to the presence of a substrate, which is not ideal for high-density electronic device mounting.
Innovation Solution
A capacitor design featuring an electrostatic capacitance forming portion with a first electrode/dielectric layer/second electrode structure, where the silicon portion is minimized to 50% or less in the lower portion, allowing for a smaller thickness and higher capacitance by positioning the silicon on the sides of the capacitance forming portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a substrate is present on a first principal surface of the capacitor to achieve high electrostatic capacitance, then the electrostatic capacitance is improved, but the thickness of the capacitor increases
Solution Approach 1:
The patent transitions from a planar substrate-based capacitor structure to a three-dimensional stacked capacitor structure. Multiple capacitor elements are stacked vertically with upper and lower electrodes alternating with dielectric layers, enabling high capacitance without increasing the footprint area. The capacitor elements extend in the thickness direction rather than relying on a large substrate area.
Solution Approach 2:
The patent employs a nested structure where capacitor elements are stacked within a compact volume. The upper and lower electrodes are positioned at different heights with dielectric layers in between, creating a nested arrangement of conductive and insulating layers that maximize capacitance density within the available space.
2Length of stationary object
If the thickness of the capacitor is reduced for miniaturization, then the size is improved, but the electrostatic capacitance decreases
Solution Approach 1:
The patent applies local quality by using porous metal sintered bodies with high surface area to volume ratio as electrodes. The porous structure provides large electroactive surface area within a compact thickness, enabling high capacitance without increasing the overall capacitor thickness. The dielectric layers are also optimized with appropriate thicknesses to maximize capacitance density.
Solution Approach 2:
The patent uses composite materials including porous metal sintered bodies combined with dielectric layers to achieve high capacitance in a thin profile. The combination of porous conductive materials and insulating dielectric layers creates a structure that maximizes electrostatic capacitance within minimal thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a small thickness and high electrostatic capacitance while facilitating miniaturization, enhancing the capacitor's strength and ease of integration with other electronic components.
Implementation Method 1
an electrostatic capacitance forming portion having a first electrode/dielectric layer/second electrode structure
Data Source
AI summary
A capacitor is provided that includes an electrostatic capacitance forming portion with a first electrode/dielectric layer/second electrode structure, and a silicon portion. Moreover, the silicon portion is disposed on at least a part of a side of the electrostatic capacitance forming portion. When the capacitor is viewed in a thickness direction thereof, a region occupied by the silicon portion in a lower portion of the electrostatic capacitance forming portion is 50% or less.