Semiconductor Capacitor with Metal Silicide Electrode and Planarized Structure
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high process compatibility between capacitor elements and MIS transistors, leading to complex fabrication steps, impurity profile fluctuations, and unstable capacitor characteristics due to etch-back processes and planarity issues.
Innovation Solution
A semiconductor device with a capacitor element featuring a metal silicide lower electrode, a first insulating film, and a planarized metal upper electrode, where the capacitor element's upper surface is flush with a second insulating film, allowing for simultaneous formation with MIS transistors and improved planarity, using metal silicide films like NiSi or Ni2Si and nickel metal films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor element is formed after the MIS transistor using conventional steps, then the capacitor element can be formed with separate process control, but the fabrication steps become complicated and thermal processes cause impurity profile fluctuations
Solution Approach 1:
The patent merges the capacitor element formation process with the MIS transistor formation process by forming both structures simultaneously in the same fabrication steps. The gate electrode of the MIS transistor and the lower electrode of the capacitor element are formed together, and subsequent processing steps are coordinated to complete both structures, thereby simplifying the overall fabrication process while maintaining transistor characteristics stability through avoided thermal processes.
Solution Approach 2:
The patent applies preliminary action by forming the gate electrode and lower electrode simultaneously in advance, and preparing the insulating film structure beforehand to enable subsequent capacitor formation without additional thermal processing. This preliminary coordination of structures prevents later thermal processes that would cause impurity profile fluctuations.
2Device complexity
If the capacitor element is formed simultaneously with the MIS transistor to simplify steps, then fabrication complexity is reduced, but planarity issues and etch-back damage occur
Solution Approach 1:
The patent applies local quality by forming the insulating film with different thicknesses in different regions: a first insulating film portion with greater thickness in the capacitor element region and a second insulating film portion with lesser thickness in the MIS transistor region. This localized differentiation enables subsequent selective removal to achieve planar upper surfaces for both structures without etch-back damage, maintaining manufacturing precision while simplifying fabrication steps.
3Adaptability or versatility
If etch-back process is used to form the capacitor insulating film, then the capacitor element can be formed with integrated process, but the capacitor characteristics become unstable due to process damage
Solution Approach 1:
The patent extracts the problematic etch-back process from the fabrication sequence by using selective removal of the first insulating film portion instead. The capacitor insulating film is formed by depositing a new insulating film on the lower electrode after selective removal, avoiding the damage caused by etch-back processes while maintaining process compatibility for integrated capacitor and transistor formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies fabrication steps, enhances the planarity of capacitor elements, maintains transistor characteristics, and prevents impurity profile fluctuations, while ensuring compatibility with MIS transistors and reducing fabrication costs.
Implementation Method 1
a lower electrode made of a metal silicide film formed on an isolation region provided in a semiconductor substrate
Implementation Method 2
the capacitor element portion has an upper surface planarized to be flush with an upper surface of the second insulating film
Data Source
AI summary
After a capacitor forming portion is formed on a semiconductor substrate by patterning an insulating film and a silicon film, a sidewall insulating film is formed on each of the side surfaces of the capacitor forming portion. Then, the insulating film is selectively removed such that the silicon film is exposed in a depressed portion surrounded by the sidewall insulating film. Subsequently, a first metal film is deposited and then a thermal process is performed to change the silicon film into a first metal film. Thereafter, an insulating film and a second metal film are buried in the depressed portion. The insulating film composes the capacitor insulating film of a capacitor element. The first metal silicide film and the second metal film compose the lower and upper electrodes of the capacitor element, respectively.