Capacitor Stack Etching With Single-Mask Stair-Step Alignment
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Solution Overview
Problem
Existing methods for fabricating integrated circuits with capacitors are inefficient, leading to high manufacturing costs due to the need for multiple photolithography steps and the formation of conductive residues that can cause shorting, which increases the chances of capacitor failure.
Innovation Solution
A method involving successive steps of forming a stack with conductive and dielectric layers, using chlorinated and fluorinated physicochemical plasma etching to create stair steps without etching the substrate, and a single photolithography step to reduce manufacturing costs and prevent shorting, along with a stripping process to remove residues using a specific solvent.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography steps are used to fabricate the capacitor, then the manufacturing precision and alignment of layers are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple photolithography steps into a single photolithography step by using a specific etching sequence with chlorinated and fluorinated plasmas. The single photolithography step creates a masking layer that guides both the first etching operation (forming the cavity) and the second etching operation (forming the electrode), thereby reducing process complexity while maintaining alignment precision through the sequential etching steps
2Productivity
If conventional etching methods are used, then the etching speed is maintained, but conductive residues are formed on the etched surfaces causing shorting
Solution Approach 1:
The patent changes the chemical parameters of the etching process by using specific chlorinated and fluorinated plasma compositions. The chlorinated plasma etches the dielectric layer while the fluorinated plasma etches the electrode, and this parameter change prevents the formation of conductive residues by controlling the chemical reactions at the etching front, thereby maintaining high etching speed without generating harmful conductive byproducts
Solution Approach 2:
The patent converts the potential harm of aggressive plasma etching (which could leave conductive residues) into a benefit by carefully selecting the plasma chemistry. The chlorinated and fluorinated plasmas are aggressive enough to maintain high etching speeds but are chemically tuned to produce non-conductive etching byproducts, thus converting what could be a harmful process into a beneficial one that simultaneously achieves high productivity and residue-free surfaces
3Shape
If the etching is stopped within the dielectric layer, then the capacitor structure with stair steps is formed, but the manufacturing precision requires precise control of etching depth
Solution Approach 1:
The patent segments the etching process into two distinct sequential steps: first, a chlorinated plasma etches the dielectric layer to a controlled depth to form the cavity; second, a fluorinated plasma etches the electrode material. This segmentation allows each etching step to be independently controlled and optimized, with the first step creating the stair step structure by stopping within the dielectric layer, and the second step completing the electrode formation without requiring complex single-step depth control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the number of photolithography steps, minimizes the formation of conductive residues, and lowers manufacturing costs by creating a capacitor structure with aligned layers and electrodes, thereby reducing the chances of shorting and improving the reliability of the capacitor.
Implementation Method 1
etching by a chlorinated physicochemical plasma etching, through said masking layer, a top part of the stack
Implementation Method 2
etching by a fluorinated physicochemical plasma etching, through said masking layer, a bottom part of the stack
Data Source
AI summary
The present disclosure relates to a method of fabricating a capacitor, comprising the following successive steps of: a) forming a stack including, in order from the top face of a first conductive layer, a first electrode, a dielectric layer, a second electrode, and a second conductive layer; b) forming by photolithography, a masking layer on a face of the second conductive layer opposite to the second electrode; c) etching by a chlorinated physicochemical plasma etching, through said masking layer, a top part of the stack, said chlorinated physicochemical plasma etching being stopped within the dielectric layer; d) etching by a fluorinated physicochemical plasma etching, through said masking layer, a bottom part of the stack, said fluorinated physicochemical plasma etching being stopped on the top face of the first conductive layer; and e) removing the masking layer.