Capacitor Structure With Stacked Conducting Array For High Density
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Solution Overview
Problem
The existing metal-oxide-metal (MOM) capacitor structures in semiconductor integrated circuits face limitations in increasing capacitance due to the restricted overlapping area of electrode plates, which affects integration density and can lead to low breakdown voltage issues when thinning the dielectric layer.
Innovation Solution
The proposed capacitor structure incorporates a conducting array with multiple conductive pieces and contact plugs, arranged in specific patterns to maximize the overlapping area between electrodes within a given volume, enhancing capacitance while maintaining adequate breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the overlapping area of the first electrode plate and the second electrode plate is increased to improve capacitance, then the capacitance is improved, but the integration of integrated circuits is greatly reduced due to the large area required
Solution Approach 1:
The patent transitions from a planar two-dimensional electrode arrangement to a three-dimensional stacked configuration. Multiple capacitor structures are stacked vertically with intermediate electrode plates between them, enabling capacitance multiplication without proportional increases in layout area. The overlapping area is effectively extended into the vertical dimension, achieving higher capacitance density.
Solution Approach 2:
The patent implements a nested structure where multiple capacitor units are stacked within a compact vertical space. Each capacitor unit contains electrode plates and dielectric layers nested sequentially, with intermediate electrode plates serving multiple adjacent capacitors. This nested arrangement maximizes the use of vertical space to increase total capacitance while minimizing the horizontal footprint.
2Quantity of substance
If the capacitor dielectric layer is thinned to increase capacitance, then the capacitance is improved, but the breakdown voltage problem occurs
Solution Approach 1:
The patent divides the total capacitance requirement into multiple smaller capacitor units stacked in series. Each unit has its own dielectric layer with optimized thickness that balances capacitance and breakdown voltage requirements. By segmenting the overall structure, each dielectric layer can be designed with appropriate thickness to maintain reliability while contributing to the total capacitance.
Solution Approach 2:
Instead of increasing capacitance by thinning the dielectric layer in the vertical direction, the patent adds more capacitor units stacked vertically. This shifts the capacitance enhancement strategy from modifying dielectric thickness to increasing the number of parallel capacitor elements, thereby maintaining adequate dielectric thickness and breakdown voltage while achieving higher total capacitance.
3Quantity of substance
If the first electrode plate and the second electrode plate are formed with a large area to increase capacitance, then the capacitance is improved, but the integration of integrated circuits is greatly reduced
Solution Approach 1:
The patent utilizes the vertical dimension to stack multiple capacitor structures, thereby increasing total capacitance without expanding the horizontal area. This three-dimensional approach allows more capacitance to be packed into a smaller footprint, improving integration density and allowing more circuits to be integrated on the same chip area.
Solution Approach 2:
The patent combines multiple capacitor functions into a single integrated stacked structure. Multiple electrode plates and dielectric layers are merged into one compact unit that provides the cumulative capacitance of all individual capacitors. This merging reduces the total area required compared to implementing separate capacitor structures, thereby improving integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases capacitance per unit volume, reduces layout area, and improves yield by allowing for a more efficient integration of semiconductor circuits with enhanced performance and reduced parasitic resistances and inductances.
Implementation Method 1
The capacitance of a capacitor structure can be expressed as Eq (1): C≈∈A/d Where C denotes the capacitance; ∈ denotes the dielectric constant of the capacitor dielectric layer
Implementation Method 2
an insulator disposed between the electrode plates
Data Source
AI summary
A capacitor structure is disclosed. The capacitor structure includes at least a D1+ first-level array. The D1+ first-level array comprises three first D1+ conductive pieces and a second D1+ conductive piece. Two of the first D1+ conductive pieces are disposed in a first row of the D1+ first-level array, and the remaining first D1+ conductive piece and the second D1+ conductive piece are disposed in a second row of the D1+ first-level array from left to right. The adjacent first D1+ conductive pieces are connected to each other, and the first D1+ conductive pieces are not connected to the second D1+ conductive piece.