Semiconductor Capacitor Support Pattern Structure for Leakage Reduction
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Solution Overview
Problem
As semiconductor devices, such as DRAM, integrate more densely, the area of each element decreases while the required capacitance of capacitors increases, leading to challenges in maintaining reliability and capacitance due to the three-dimensional shape of lower electrodes and increased height or cylindrical shapes.
Innovation Solution
A method of manufacturing semiconductor devices involves forming a mold layer and a preliminary support layer on a substrate, removing portions to create voids and open areas, filling these with sacrificial layers, and replacing the preliminary support layers with support patterns to enhance the structure and reduce leakage current, allowing for closer capacitor placement and increased capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the area of each element is decreased to increase integration degree, then the integration density increases, but the capacitance of capacitors decreases
Solution Approach 1:
The patent transitions from planar two-dimensional capacitor layouts to three-dimensional structures by forming lower electrodes with cylindrical or pillar shapes that extend vertically from the substrate. This dimensional change allows capacitors to occupy vertical space in addition to horizontal space, thereby maintaining or increasing capacitance values even as the horizontal area per element is reduced to achieve higher integration density.
Solution Approach 2:
The patent implements a nested structure where support patterns are positioned between and around the lower electrodes, creating a hierarchical arrangement. The support patterns are embedded within the capacitor structure at multiple levels, with first support patterns at lower heights and second support patterns at higher heights, allowing compact packing while maintaining electrical isolation and structural integrity.
2Quantity of substance
If the lower electrode is given a three-dimensional shape or increased height to maintain capacitance, then the capacitance is maintained, but the manufacturing complexity increases
Solution Approach 1:
The patent forms support patterns before forming the upper electrodes, creating a pre-assembled framework that defines the final capacitor geometry. The support patterns are formed at different height levels using sequential deposition and planarization steps, establishing the three-dimensional structure in advance before the final electrode assembly, thereby simplifying subsequent manufacturing steps.
Solution Approach 2:
The patent divides the support structure into multiple discrete support patterns positioned at different height levels and locations. First support patterns are formed at lower heights between lower electrodes, while second support patterns are formed at higher heights, creating a segmented hierarchical structure that simplifies manufacturing by allowing independent formation and optimization of each support level.
3Productivity
If capacitors are placed closer together to increase integration density, then the integration density increases, but leakage current between capacitors increases
Solution Approach 1:
The patent introduces support patterns as intermediary structures positioned between adjacent lower electrodes. These support patterns act as physical barriers and electrical isolators that prevent direct interaction and leakage current between closely spaced capacitors. The support patterns are formed from insulating materials and extend vertically to bridge gaps between electrodes, enabling closer spacing while maintaining electrical isolation.
Solution Approach 2:
The patent employs composite material structures where support patterns are formed from combinations of insulating materials deposited in multiple layers. The support patterns may include different dielectric materials with complementary properties, creating a composite structure that provides both electrical isolation and mechanical support, enabling dense capacitor packing without increasing leakage current.
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes sequentially forming a mold layer and a preliminary support layer on a substrate, forming a plurality of lower electrodes through the preliminary support layer and the mold layer, removing a portion of the preliminary support layer between the plurality of lower electrodes to form a preliminary support layer pattern having an open area exposing a top surface of the mold layer, removing the mold layer to form a void between the substrate and the preliminary support layer pattern, filling the open area and the void with a sacrificial layer, and replacing the preliminary support layer pattern with a support pattern.


