Capacitor-Based Synaptic Array for Low-Power Neural Network Computing
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Solution Overview
Problem
Existing hardware-based artificial neural networks face high power consumption during learning and reasoning processes, particularly when performing vector-matrix multiplication using conductive synaptic devices like memristors.
Innovation Solution
A neuromorphic device with a capacitor-based synaptic array, where each synaptic cell has variable capacitance for weight representation, is used for matrix calculations, incorporating a word line selection unit, bit line charging unit, and bit line discharging unit controlled by a control unit to perform operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conductive synaptic devices like memristors are used for vector-matrix multiplication, then hardware-based neural network functionality is achieved, but power consumption increases significantly
Solution Approach 1:
The patent changes the fundamental parameter used for weight representation from conductance (in memristors) to capacitance (in capacitor-based synaptic cells). This parameter change allows the system to perform vector-matrix multiplication with significantly reduced power consumption while maintaining the hardware-based neural network functionality, as capacitive devices consume less power during read operations compared to resistive devices
Solution Approach 2:
The patent substitutes the resistive mechanism (Ohm's law) with a capacitive mechanism. Instead of using conductive synaptic devices that rely on resistive properties for weight storage and multiplication, the invention uses capacitor-based synaptic cells that store weights as capacitance values, fundamentally changing the physical mechanism underlying the computation and reducing power consumption
2Use of energy by moving object
If conventional von Neumann architecture is used with software-based neural networks, then flexibility and programmability are maintained, but energy consumption increases during learning and reasoning processes
Solution Approach 1:
The patent segments the neural network computation into distinct hardware components: capacitor-based synaptic cells for weight storage, word line selection units for row selection, and bit line charging/discharging units for column operations. This segmentation allows specific hardware modules to handle specific computational tasks, reducing overall energy consumption while maintaining the ability to implement different neural network architectures through configuration rather than physical reconfiguration
Solution Approach 2:
The capacitor-based synaptic array is designed to be universal, capable of performing various neural network operations including vector-matrix multiplication, weight storage, and computation. The same hardware structure can be configured to implement different neural network models and algorithms, providing both energy efficiency and adaptability
3Loss of energy
If capacitor-based synaptic cells are used for matrix calculations, then power consumption and leakage current are reduced, but additional control circuitry is required
Solution Approach 1:
The patent merges the control functions into integrated units: the word line selection unit combines multiple switching elements that control word lines, and the bit line charging/discharging units integrate multiple switching elements for bit line control. This merging reduces the overall control circuit complexity compared to having separate control circuits for each synaptic cell, while still enabling precise control of the capacitor-based synaptic array
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and leakage current, enhancing the performance and accuracy of matrix calculations in artificial neural networks by leveraging the adjustable capacitance of capacitor-based synaptic cells.
Implementation Method 1
a synaptic array including a plurality of capacitor-based synaptic cells, each having a variable capacitance according to a recorded weight
Implementation Method 2
a bit line charging unit including a plurality of switching elements, each being connected to one end of each of bit lines of the synaptic array, and a bit line discharging unit including a plurality of switching elements, each being connected to the other end of each of the bit lines of the synaptic array
Data Source
AI summary
A hardware-based artificial neural network device includes a synaptic array including a plurality of capacitor-based synaptic cells, each having a variable capacitance according to a recorded weight, a word line selection unit including a plurality of switching elements respectively connected to word lines of the synaptic array, a bit line charging unit including a plurality of switching elements, each being connected to one end of each of bit lines of the synaptic array, and a bit line discharging unit including a plurality of switching elements, each being connected to the other end of each of the bit lines of the synaptic array.