Stacked Capacitor-Transistor Memory Cell for Reduced Cell Area
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, integration, reliability, reading accuracy, on-state current, electrical characteristics, power consumption, and operation speed, particularly in memory devices where the area occupied by transistors and capacitors increases, limiting their density and performance.
Innovation Solution
A semiconductor device architecture that includes a capacitor and two transistors stacked in a specific configuration, with conductive and insulating layers arranged to minimize area usage, utilizing metal oxide semiconductor layers with indium, zinc, and other elements to enhance capacitance and electrical properties, allowing for high integration and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors and capacitors are arranged in conventional planar configuration, then manufacturing and wiring are simplified, but the area occupied by each memory cell increases, limiting integration density
Solution Approach 1:
The patent transitions from conventional planar arrangement to a three-dimensional stacked configuration where transistors and capacitors are vertically stacked. The capacitor is positioned directly over the transistor with conductive layers extending vertically, enabling memory cells to occupy significantly reduced planar area while maintaining functionality through vertical interconnections.
Solution Approach 2:
The patent implements nesting by placing the capacitor structure directly over the transistor structure, with the capacitor's first conductive layer positioned over the transistor's drain electrode. The second conductive layer of the capacitor extends downward to contact the first conductive layer, creating a nested vertical arrangement that maximizes space utilization.
2Reliability
If oxide semiconductor materials are used in transistors, then leakage current is reduced and reliability improves, but manufacturing complexity and material processing difficulty increase
Solution Approach 1:
The patent specifies precise compositional parameters for the oxide semiconductor layer, including atomic ratios of indium to zinc between 1:4 and 4:1, and controlled addition of gallium (0.1-5 atomic %) and tin (0.1-5 atomic %). These parameter controls enable reliable low-leakage performance while maintaining manufacturability through defined material specifications.
Solution Approach 2:
The patent employs composite oxide semiconductor materials combining multiple elements (In-Zn-Ga-Sn-O system) to achieve superior electrical characteristics. The multi-element composition provides both low leakage current and appropriate carrier concentration, balancing reliability with processability through synergistic material properties.
3Reliability
If metal oxide semiconductor layers with specific compositions are used, then capacitance and electrical properties are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent defines specific atomic ratio ranges for oxide semiconductor materials (In:Zn = 1:4 to 4:1, Ga = 0.1-5 atomic %, Sn = 0.1-5 atomic %) that balance electrical performance with manufacturing feasibility. These parameter specifications enable consistent electrical characteristics while accommodating normal process variations.
Solution Approach 2:
The patent applies different material compositions to different functional regions: the oxide semiconductor layer uses specific In-Zn-Ga-Sn ratios for optimal transistor performance, while the capacitor dielectric layer uses separate material composition optimized for capacitance. This local optimization achieves high electrical performance without requiring extreme precision across all layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of highly integrated, reliable, and high-capacity memory devices with improved reading accuracy, on-state current, and reduced power consumption, while maintaining high manufacturing yield and operational speed.
Implementation Method 1
a semiconductor device means a device that utilizes semiconductor characteristics
Implementation Method 2
a memory device, a display apparatus, a light-emitting apparatus, a lighting device, and an electronic apparatus themselves are semiconductor devices
Data Source
AI summary
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a capacitor, a transistor, and a first insulating layer. The capacitor includes first and second conductive layers and a second insulating layer. The second insulating layer is in contact with a side surface of the first conductive layer, and the second conductive layer covers at least part of the side surface of the first conductive layer with the second insulating layer therebetween. The transistor includes third to fifth conductive layers, a semiconductor layer, and a third insulating layer. The third conductive layer is in contact with a top surface of the first conductive layer. The first insulating layer is provided over the third conductive layer, and the fourth conductive layer is provided over the first insulating layer. The first insulating layer and the fourth conductive layer include an opening portion reaching the third conductive layer. The semiconductor layer is in contact with the third and fourth conductive layers. The semiconductor layer includes a region positioned inside the opening portion. Over the semiconductor layer, the third insulating layer and the fifth conductive layer are provided in this order so as to each include a region positioned inside the opening portion.