Capacitor Triggered SCR for Submicron ESD Protection

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Solution Overview

Problem

Current ESD protection circuits for semiconductor devices are inadequate for technologies less than 65 nm, as they have slow trigger times and high trigger voltages, which can cause damage to thin gate dielectrics and are insufficient for fast ESD events like those described by the Charged Device Model (CDM).

Innovation Solution

A fast capacitor-triggered SCR ESD protection circuit is developed, utilizing a PNPN type SCR formed in a P-substrate with a gated-diode and MOS capacitor trigger device, allowing for independent setting of trigger current and voltage through layout parameters, and featuring a low trigger voltage to protect thin oxides.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ESD protection circuits are used, then protection function is provided, but trigger time is slow and trigger voltage is high

Engineering Contradiction:

ImproveESD protection capabilityVSAvoidtrigger time

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by pre-charging a capacitor through a diode during normal operation. When an ESD event occurs, the capacitor is already charged and can immediately discharge through the SCR to trigger rapid protection, eliminating the delay associated with conventional trigger mechanisms. This pre-positioning of energy enables the circuit to respond instantaneously to ESD events while maintaining low trigger voltage through the capacitor's voltage division effect.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If conventional ESD protection circuits are used, then protection function is provided, but trigger voltage is high which can damage thin gate dielectrics

Engineering Contradiction:

ImproveESD protection capabilityVSAvoiddamage to thin gate dielectrics

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a capacitor as an intermediary element between the ESD event and the SCR trigger mechanism. This capacitor acts as a voltage divider that reduces the trigger voltage presented to the SCR, allowing it to stay below the breakdown voltage of thin gate dielectrics. The capacitor mediates the energy transfer, enabling the SCR to trigger at safe voltage levels while still providing effective ESD protection.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If conventional ESD protection circuits are used, then protection function is provided, but additional manufacturing steps are required

Engineering Contradiction:

ImproveESD protection capabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the ESD protection function with existing circuit elements by implementing the capacitor and diode trigger mechanism using standard CMOS process components. The SCR is formed using conventional bipolar transistor structures, and the triggering elements are integrated into the same fabrication process flow, eliminating the need for additional manufacturing steps or specialized process modules.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides fast triggering suitable for submicron CMOS transistors, protects very thin gate oxides, allows independent setting of trigger parameters, ensures high stability for power supply protection, and does not require additional manufacturing steps, while maintaining circuit performance.

Implementation Method 1

a MOS capacitor trigger device

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

providing a low-impedance path to safely shunt an ESD charge to VSS

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

a FET configured to trigger the SCR into conduction

Methodology Applied

Scientific EffectField effect transistor operation:

Data Source

PatentUS8129788B1Capacitor triggered silicon controlled rectifier

Publication Date: 2012.03.06 CYPRESS SEMICONDUCTOR CORP

AI summary

A protection circuit and method are provided for protecting semiconductor devices from electrostatic discharge (ESD). Generally, the ESD protection circuit includes a silicon controlled rectifier (SCR) formed in a substrate and configured to transfer charge from a protected node to a negative power supply, VSS, during an ESD event, and a trigger device to activate transfer of charge by the SCR when a voltage on the protected node reaches a predetermined trigger voltage. The trigger device includes a gated-diode and MOS capacitor formed in a well formed in the substrate, the trigger device configured to inject electrons into the well during charging of the MOS capacitor, forward biasing a node of the SCR, hence allowing fast triggering of the SCR device. The trigger voltage can be set independent of a holding voltage by adjusting the length of the well and area of the capacitor. Other embodiments are also disclosed.