Capacitor Via Etching Compensation for Wafer-Edge Tilt
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Solution Overview
Problem
During the manufacturing of Dynamic Random Access Memory (DRAM) capacitors, the high aspect ratio etching process often results in tilted capacitor vias at the edge of the wafer, leading to defects and a risk of short circuits due to inability to butt the capacitor with the landing pad.
Innovation Solution
A method involving compensated etching parameters is used to form capacitor vias, where the first and second mask layers are etched in specific directions to mitigate tilt, allowing successful alignment with the landing pad, thereby preventing short circuits and enhancing production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high aspect ratio etching is used to increase capacitor density, then capacitor miniaturization is achieved, but capacitor via tilt occurs at wafer edge
Solution Approach 1:
The patent applies preliminary anti-action by introducing a compensation amount in the etching parameters before the etching process begins. This compensation amount is calculated based on the distance from the wafer center, and it pre-corrects for the plasma distribution non-uniformity that would otherwise cause via tilt. By anticipating and counteracting the expected deviation, the method ensures that capacitor vias are properly aligned with landing pads even at wafer edges, preventing short circuits while maintaining high aspect ratio etching for capacitor miniaturization
2Productivity
If conventional etching parameters are used, then etching speed is maintained, but capacitor via tilt occurs leading to alignment failure
Solution Approach 1:
The patent implements parameter changes by modifying the etching parameters based on the spatial position on the wafer. A compensation amount is added to the etching parameters, and this compensation varies according to the distance from the wafer center. This allows the etching process to maintain high speed while achieving proper via alignment, as the parameter adjustment compensates for plasma distribution non-uniformity without significantly impacting overall etching throughput
Data Source
AI summary
A method for forming a capacitor via includes: providing a to-be-processed wafer, the to-be-processed wafer including a substrate and a first dielectric layer and a first mask layer that are sequentially formed on a surface of the substrate; etching the first mask layer according to a compensated first etching parameter, to form a first patterned layer extending in a first etching direction; sequentially forming a second dielectric layer and a second mask layer on a surface of the first patterned layer; etching the second mask layer and the second dielectric layer according to a compensated second etching parameter, to form a second patterned layer extending in a second etching direction; and etching the first dielectric layer with the first patterned layer and the second patterned layer together as a capacitor pattern, to form a capacitor via.