Capacitor-Weighted Segmentation Buffer for Low-Power Accurate DAC Drive
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Solution Overview
Problem
Existing buffer circuits face challenges with high power consumption, large chip area, and low accuracy, particularly in applications like convolutional neural networks and compute-in-memory circuits, where conventional solutions are neither power-efficient nor provide high accuracy.
Innovation Solution
A capacitor weighted segmentation buffer is introduced, incorporating a push-pull buffer circuit and capacitors with varying capacitance values, which operates in discrete-time modes to stabilize performance across process, voltage, and temperature variations, allowing integration with digital-to-analog converters for reduced energy and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a conventional buffer circuit is used, then the circuit can operate, but it suffers from high power consumption and large chip area
Solution Approach 1:
The buffer circuit is segmented into multiple parallel paths with different gain weights (e.g., full-gain path and half-gain path). Each path processes a portion of the input signal, and the results are combined. This segmentation allows the circuit to achieve high accuracy through weighted summation while maintaining low power consumption by activating only necessary paths based on input requirements.
2Stability of the object's composition
If a closed-loop buffer is used to achieve stability, then phase margin performance is improved, but speed and energy consumption worsen
Solution Approach 1:
The buffer circuit employs dynamic path selection where the gain configuration can be adjusted based on operating conditions. The circuit can switch between different gain paths (full-gain, half-gain) dynamically, allowing it to optimize for speed when stability is less critical and for accuracy when stability is required, without being locked into a fixed closed-loop configuration.
3Adaptability or versatility
If separate DAC and buffer circuits are used, then functionality is complete, but chip area increases
Solution Approach 1:
The buffer circuit is designed with integrated DAC functionality by sharing the capacitor array between the DAC and buffer operations. The same capacitors used for digital-to-analog conversion are also utilized for the buffered output with different gain weights, eliminating the need for separate dedicated components and reducing overall chip area while maintaining full functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitor weighted segmentation buffer achieves low power consumption, ultra-small area, and high accuracy by stabilizing gain across PVT variations, enabling efficient integration with DACs and reducing complexity in AI applications.
Implementation Method 1
The capacitors include a first capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal arranged to receive a first input signal of the capacitor weighted segmentation buffer; a second capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal arranged to receive the first input signal of the capacitor weighted segmentation buffer
Data Source
AI summary
A capacitor weighted segmentation buffer includes a push-pull buffer circuit and a plurality of capacitors. The capacitors include a first capacitor having a first terminal coupled to a control terminal of the first transistor and a second terminal arranged to receive a first input signal; a second capacitor having a first terminal coupled to a control terminal of the second transistor and a second terminal arranged to receive the first input signal; a third capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal arranged to receive a second input signal; and a fourth capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal arranged to receive the second input signal.