Capacitorless 1T DRAM Cell With Floating Body And Interconnected Gates
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Solution Overview
Problem
Conventional DRAM cells rely on storage capacitors, which require frequent refresh operations and consume power, whereas capacitorless one transistor DRAM cells aim to reduce power consumption by utilizing a floating body effect in semiconductor-on-insulator transistors, but face challenges in efficient formation and integration into arrays.
Innovation Solution
The method involves forming capacitorless one transistor DRAM cells by creating spaced islands of semiconductive material on a semiconductor substrate, with a floating body region and conductive gates, using insulative materials and patterning techniques to create interconnected gate lines and separate control over word and gate lines, allowing for efficient data storage and retrieval without capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional DRAM cells with storage capacitors are used, then data storage capability is achieved, but power consumption increases and frequent refresh operations are required
Solution Approach 1:
The patent removes the storage capacitor component from the traditional DRAM cell structure, extracting only the essential transistor element. This eliminates the need for capacitor-based charge storage while maintaining data storage functionality through the floating body effect in the transistor, thereby reducing power consumption and refresh operations
Solution Approach 2:
The patent changes the operational parameter from capacitor charge storage to floating body charge accumulation. By utilizing the body effect in the transistor where charge accumulates in the floating body region rather than in a separate capacitor, the system achieves data storage with different physical mechanisms that consume less power
2Use of energy by moving object
If capacitorless one transistor DRAM cells are used, then power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the manufacturing process into distinct patterning stages, using separate mask layers for forming word lines and gate lines. This segmentation allows each layer to be optimized independently while maintaining overall process simplicity, addressing the manufacturing complexity challenge
Solution Approach 2:
The patent introduces a vertical dimension to the gate structure by forming gates that extend over the floating body region from above, rather than lateral gating. This dimensional change simplifies the overall cell structure and manufacturing while enabling the capacitorless operation
3Productivity
If capacitorless one transistor DRAM cells are used, then device integration density is improved, but operational complexity increases
Solution Approach 1:
The transistor structure serves multiple functions: it acts as both the access switch and the storage element through its floating body effect. This multi-functionality reduces the number of components needed per bit, improving integration density while the control mechanisms remain relatively simple through standard transistor gating
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the development of power-efficient DRAM cells with reduced refresh operations, improving memory performance and integration into arrays while minimizing power consumption and operational complexity.
Implementation Method 1
One type of such cell utilizes a floating body effect of a semiconductor-on-insulator transistor
Implementation Method 2
The body region of the transistor is electrically floating in view of insulation or a non-conductive region disposed beneath the body region
Data Source
AI summary
This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.