Capacitorless 2-Transistor Cell Layout for Scalable 3D Memory
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Solution Overview
Problem
Existing memory technologies face challenges in achieving good retention and scalability, particularly in vertical three-dimensional memory devices, due to the presence of storage capacitors that can limit performance and efficiency.
Innovation Solution
The implementation of two transistor cells with horizontally oriented transistors and a shared source/drain region, integrated with vertically oriented access lines and horizontally oriented digit lines, eliminates the need for storage capacitors, enhancing retention and scalability in vertical three-dimensional memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If storage capacitors are used in vertical three-dimensional memory, then data storage function is achieved, but retention and scalability are limited
Solution Approach 1:
The patent extracts and removes the storage capacitor component from the memory cell structure, transitioning from a 1T1C (one transistor one capacitor) or 2T2C structure to a capacitorless 2T cell. This extraction eliminates the scalability and retention limitations associated with capacitor technology while preserving the essential data storage function through alternative transistor-based mechanisms.
Solution Approach 2:
The patent changes the fundamental operating parameters of the memory cell by eliminating the capacitor element and modifying the transistor configuration. The cell uses two transistors with shared source/drain regions and specific gate control mechanisms to achieve data storage without capacitors, fundamentally altering how data is retained in the memory structure.
2Quantity of substance
If storage capacitors are included in memory cells, then data storage is enabled, but scalability is restricted
Solution Approach 1:
By removing the storage capacitor from the memory cell architecture, the patent enables higher memory density and scalability. The capacitorless design reduces the area required per memory cell and simplifies the fabrication process, allowing for more cells to be packed into the same physical space without the complexity of integrating and scaling capacitor structures.
3Productivity
If vertically oriented access lines and horizontally oriented digit lines are integrated with horizontally oriented transistors, then scalability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs different dimensional orientations for various components: transistors are horizontally oriented, access lines are vertically oriented, and digit lines are horizontally oriented. This multi-dimensional arrangement allows for efficient scaling in both vertical and horizontal directions, optimizing memory density while managing manufacturing complexity through systematic spatial organization.
Data Source
AI summary
Systems, methods and apparatus are provided for two transistor cells for vertical three-dimensional memory. The memory has serially connected horizontally oriented transistors each having an independent first source/drain region and a shared second source/drain region separated by channel regions, and gates opposing the channel regions and separated therefrom by a gate dielectric;pairs of vertically oriented access lines coupled to the gates and separated from the channel region by the gate dielectric; and horizontally oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented transistors.