Capacitorless DRAM Active Pillar Gate Pattern
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Solution Overview
Problem
The integration density of dynamic random access memory (DRAM) devices is limited by the short-channel effect and high manufacturing costs associated with complex capacitor formation techniques, which hinder further miniaturization and increase production expenses.
Innovation Solution
A semiconductor memory device design featuring active pillars projecting from a semiconductor substrate with a gate pattern and conductive lines, where the gate pattern surrounds the active pillars and the conductive lines are insulated from the substrate, allowing for improved integration density and reduced manufacturing costs by eliminating the need for expensive substrates like SOI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is shrunk to improve integration density, then integration density is improved, but short-channel effect occurs
Solution Approach 1:
The gate pattern extends in multiple directions (e.g., three-dimensional or multi-directional gating) around the active pillar, transitioning from conventional planar gating to spatially distributed gating. This dimensional change allows better control of the channel region without further shrinking the transistor footprint, thereby improving integration density while suppressing short-channel effects through enhanced electrostatic control.
Solution Approach 2:
The gate pattern is configured to surround or partially surround the active pillar in a nested arrangement, with the gate structure enveloping the channel region from multiple sides. This nesting configuration provides superior electrostatic control over the channel compared to conventional top-only gating, enabling smaller device dimensions without suffering from short-channel effects.
2Productivity
If complex capacitor formation techniques are employed to improve integration density, then integration density is improved, but manufacturing costs increase
Solution Approach 1:
The invention extracts or eliminates the capacitor component from the traditional DRAM cell structure, transitioning to a capacitorless design where data is stored directly in the transistor's channel region or body region. This removal of the capacitor simplifies the cell structure, reduces manufacturing process complexity, and lowers production costs while maintaining high integration density through the novel gate pattern configuration.
Solution Approach 2:
The gate pattern serves multiple functions simultaneously: it controls the channel for transistor operation, provides data storage capability through charge accumulation in the body region, and enables capacitorless DRAM functionality. This multi-functionality eliminates the need for separate capacitor structures and complex formation techniques, thereby reducing manufacturing costs while achieving high integration density.
3Reliability
If gate pattern vertical thickness is adjusted to suppress short-channel effect, then short-channel effect is suppressed, but device structure becomes more complex
Solution Approach 1:
Instead of solely increasing vertical gate thickness to suppress short-channel effects, the invention employs multi-directional or three-dimensional gate patterns that extend laterally around the active pillar. This dimensional change provides enhanced electrostatic control through increased gate-to-channel interface area without requiring excessive vertical thickness, thereby suppressing short-channel effects while maintaining relatively simple gate structure fabrication.
Data Source
AI summary
Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a plurality of active pillars projecting from a semiconductor substrate, a gate pattern disposed on at least a portion of each of the active pillars with a gate insulator interposed therebetween, and a conductive line disposed on each of the active pillars and below the corresponding gate pattern, the conductive line may be insulated from the semiconductor substrate and the gate pattern, wherein each of the active pillars may include a drain region above the corresponding gate pattern, a body region adjacent to the corresponding gate pattern, and a source region that is in contact with the conductive line below the gate pattern.