Capacitorless DRAM Cell Heterostructure Segmentation
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Solution Overview
Problem
Current DRAM cells are limited by their external capacitor size, and there is a need to increase hole retention time and drain-to-source current while scaling down the memory cell size, as recombination rates increase with charge carrier density, making it challenging to achieve market viability.
Innovation Solution
A capacitorless DRAM cell design utilizing a heterostructure with alternating semiconducting channel and electrically insulating barrier layers, where the barrier layers suppress charge carrier loss by preventing movement across them, allowing for increased retention time and improved scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the memory cell size is scaled down, then the integration density increases, but the hole retention time decreases due to increased recombination rates
Solution Approach 1:
The channel is segmented into multiple sub-channels separated by barrier layers, creating distinct regions for hole storage and transport. This segmentation allows holes to be confined in specific channel regions, reducing recombination losses and maintaining retention time even as overall cell size decreases
Solution Approach 2:
Different regions of the channel are given different properties through the alternating channel-barrier structure. The channel layers have high carrier mobility for transport, while the barrier layers have low carrier concentration for confinement, creating local quality variations that optimize both retention and scaling
2Power
If the charge carrier density is increased to improve current, then the recombination rate increases, reducing retention time
Solution Approach 1:
The channel is divided into multiple sub-channels separated by barrier layers, creating distinct regions for hole storage and transport. This segmentation allows holes to be confined in specific channel regions, reducing recombination losses and maintaining retention time even as overall cell size decreases
Solution Approach 2:
The barrier layers act as intermediary structures between channel regions, providing controlled interfaces that manage carrier flow. These barriers mediate the trade-off between current and retention by allowing sufficient carrier injection for high current while preventing excessive accumulation that would increase recombination
3Area of moving object
If a traditional 1T1C structure is used, then the cell area is relatively large, but the scalability is limited by the capacitor size
Solution Approach 1:
The external capacitor is extracted from the traditional 1T1C structure, eliminating the large capacitive component that limited scaling. The hole storage function is transferred to the channel-barrier heterostructure itself, enabling significant reduction in cell area and improved scalability
Solution Approach 2:
The storage and transport functions are merged into a single channel-barrier heterostructure rather than being separated into distinct capacitor and transistor components. This integration eliminates the need for large external capacitors and enables continued scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitorless DRAM cell design enhances charge carrier retention time and drain-to-source current, enabling further miniaturization and potentially increasing the efficiency of memory storage and read/write cycles.
Implementation Method 1
each barrier layer is electrically insulating and may thus prevent transport of the charge carriers across the barrier layer
Implementation Method 2
depending on the configuration of voltages applied to the adjacent source, gate and drain structures, may allow either storage of electric charge carriers (electrons and/or holes) or their transport
Data Source
AI summary
The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.