Capacitorless DRAM Cell Mitigates Word Line Coupling Noise
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Solution Overview
Problem
Capacitorless single-transistor DRAM memory cells face issues with large capacitive coupling between the word line and floating body, leading to data misreading or erroneous rewriting due to voltage swings during read or write operations, making them difficult to implement practically.
Innovation Solution
A memory device with a semiconductor element structure that includes a semiconductor base material, impurity layers, gate insulating layers, and gate conductor layers, where the channel semiconductor layer holds positive holes generated by impact ionization, and voltage control is used to manage data retention and erase operations, with specific capacitance ratios and voltage settings to minimize capacitive coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitorless single-transistor DRAM memory cell is used, then device complexity is reduced and packaging density is improved, but capacitive coupling noise between word line and floating body increases causing data misreading
Solution Approach 1:
The patent introduces a lightly-doped drain (LDD) region as an intermediary structure between the channel and the floating body. This LDD region acts as a buffer that reduces the direct capacitive coupling between the word line and the floating body, thereby minimizing noise transmission while preserving the capacitorless single-transistor memory cell structure.
Solution Approach 2:
The patent applies different doping concentrations to different regions: the channel region has a specific doping level for proper transistor operation, while the LDD region has a lighter doping concentration. This local variation in doping quality creates an electrical gradient that reduces capacitive coupling effects in the critical interface region between the channel and floating body.
2Ease of operation
If voltage swings are applied during read or write operations, then data writing and reading operations are enabled, but capacitive coupling causes erroneous rewriting or misreading
Solution Approach 1:
The lightly-doped drain region is constructed in advance during the manufacturing process to provide electrical buffering. This pre-established structure cushions against the harmful effects of voltage swings during subsequent read and write operations, preventing erroneous data changes before they can occur.
Solution Approach 2:
The LDD region serves as an intermediary that decouples the voltage swings from the floating body. When voltage is applied to the word line for read or write operations, the LDD region absorbs and attenuates the capacitive coupling effects, allowing operations to proceed without causing erroneous data retention changes.
3Quantity of substance
If floating body is used to store data, then capacitorless operation is achieved, but capacitive coupling with word line causes noise transmission
Solution Approach 1:
The LDD region is introduced as an intermediary structure between the channel and the floating body. This intermediary layer reduces the direct capacitive coupling path, thereby minimizing noise transmission from the word line to the floating body while preserving the capacitorless memory cell architecture.
Solution Approach 2:
By creating a region with lighter doping concentration (the LDD region) at the critical interface between the channel and floating body, the patent locally modifies the electrical properties to reduce capacitive coupling. This local quality change allows the floating body to store data effectively without excessive noise from the word line.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces capacitive coupling noise, ensuring a sufficient potential difference between logic states during writing and reading, thereby enhancing the reliability and practicality of capacitorless DRAM memory cells.
Implementation Method 1
a positive hole group generated by an impact ionization phenomenon is held in the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer
Data Source
AI summary
A page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer of a memory cell and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer. a refresh operation is performed to return the voltage of the channel semiconductor layer of a selected word line to a first data retention voltage thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer of the memory cell in which a voltage of the channel semiconductor layer is set to the first data retention voltage using the page write operation. The refresh operation is performed, with a switch circuit kept in a nonconducting state, concurrently with a page read operation of reading page data of a first memory cell group belonging to a first page.