Capacitor-less DRAM with Dual Gate Control for Noise Reduction
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face challenges due to strong capacitive coupling between the word line and the floating body, leading to erroneous reading or rewriting of storage data, which hinders commercial introduction.
Innovation Solution
A semiconductor-element-including memory device is designed with a structure where each memory cell includes a semiconductor body, impurity regions, a gate insulator layer, and gate conductor layers. The device controls voltages to retain positive holes generated by impact ionization within the semiconductor body, allowing for independent control of pages and reducing capacitive coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but capacitive coupling noise between word line and floating body increases causing erroneous reading or rewriting
Solution Approach 1:
The gate conductor layer is divided into two separate layers: a first gate conductor layer connected to the word line and a second gate conductor layer connected to a control line. This segmentation allows independent control of the two gate layers, enabling the second layer to compensate for capacitive coupling noise from the word line, thus improving data reading accuracy while maintaining high integration density
Solution Approach 2:
The second gate conductor layer acts as an intermediary element between the word line and the floating body. By controlling the voltage of the second gate layer through a control line, it serves as a mediator to counteract the unwanted capacitive coupling effects from the word line, preventing erroneous reading or rewriting of stored data
2Device complexity
If strong capacitive coupling between word line and floating body is present, then device structure is simplified, but operational margin between '1' and '0' states decreases
Solution Approach 1:
The patent introduces dynamic control of the second gate conductor layer voltage through a control line. This allows the gate structure to adapt dynamically to different operating conditions, adjusting the voltage on the second gate layer to optimize the operational margin between '1' and '0' states while maintaining the simplified capacitor-less structure
Solution Approach 2:
By independently controlling the voltage parameter of the second gate conductor layer through the control line, the patent changes the electrical parameters of the memory cell to enhance the operational margin. This parameter control allows optimization of read and write operations without increasing structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces capacitive coupling noise, enhancing the operational margin between '1' and '0' states, thereby improving the reliability and performance of capacitor-less single-transistor DRAMs.
Implementation Method 1
a group of positive holes, generated by an impact ionization phenomenon, are retained inside the semiconductor body by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region
Data Source
AI summary
A memory device includes pages including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes. The first and second impurity regions and first and second gate conductor layers are connected to source, bit, plate, and word lines. In a page write operation, a channel semiconductor layer is at a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the channel semiconductor layer is at a second data retention voltage, a positive voltage pulse is applied to at least one of the word and plate lines of a selected page, and a ground voltage is applied to the word and plate lines of a non-selected page and to all of the source and bit lines.