Capacitor-less DRAM Gate Segmentation for Noise Reduction
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face challenges due to strong capacitive coupling between the word line and the floating body, leading to noise interference and erroneous data reading or writing, which hinders commercial adoption.
Innovation Solution
The memory device employs a structure where a plurality of memory cells are arranged in a column direction, each comprising a semiconductor body with impurity layers and gate insulator and conductor layers. By controlling voltages applied to these layers, positive holes generated by impact ionization are retained or discharged, allowing for data retention and erasure without a capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but strong capacitive coupling between word line and floating body causes noise interference and erroneous data reading/writing
Solution Approach 1:
The patent divides the gate control into two independent gate electrodes (first gate electrode and second gate electrode) that can be controlled separately. This segmentation allows independent optimization of write operation (using first gate electrode) and read operation (using second gate electrode), preventing the capacitive coupling noise from affecting both operations simultaneously while maintaining high integration density.
Solution Approach 2:
The patent applies different control strategies to different parts of the gate structure. The first gate electrode is optimized for write operations with specific voltage conditions, while the second gate electrode is optimized for read operations. This local quality differentiation allows each gate to perform its specific function effectively, reducing noise interference during read operations while maintaining the capacitor-less structure benefits.
2Productivity
If strong capacitive coupling exists between word line and floating body, then write operation efficiency is improved, but noise interference increases causing erroneous data reading
Solution Approach 1:
By segmenting the gate into two independently controllable electrodes, the patent enables the first gate electrode to maintain strong capacitive coupling for efficient write operations, while the second gate electrode can be independently controlled to minimize noise during read operations, thus resolving the contradiction between write efficiency and noise reduction.
Solution Approach 2:
The patent applies different control conditions to different gate electrodes locally. The first gate electrode operates under conditions optimized for write efficiency (strong coupling), while the second gate electrode operates under conditions optimized for read accuracy (noise minimization), allowing both requirements to be satisfied simultaneously in different locations of the same device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces noise interference from word line voltage changes, enhancing the operational margin between '1' and '0' states and facilitating the commercial introduction of capacitor-less single-transistor DRAMs.
Implementation Method 1
When a high voltage is applied to both the bit line BL connected to the drain N+ layer and the word line WL connected to the gate conductor layer 105, and the MOS transistor 110 is operated at the gate voltage that is about one-half of the drain voltage, the electric field intensity becomes maximum at the pinch-off point 108 that is in the vicinity of the drain N+ layer 104. As a result, accelerated electrons that flow from the source N+ layer 103 toward the drain N+ layer 104 collide with the Si lattice, and with kinetic energy lost at the time of collision, electron-positive hole pairs are generated (impact ionization phenomenon).
Data Source
AI summary
A memory device includes pages each including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell are controlled to retain a group of positive holes. In a page write operation, a voltage of the channel semiconductor layer is made equal to a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the voltage of the channel semiconductor layer is made equal to a second data retention voltage, and erase and ground voltages are applied to selected and non-selected pages respectively. The first and second impurity layers and first and second gate conductor layers are connected to source, bit, plate, and word lines. The source, word, and plate lines are disposed parallel to the pages. The bit line is disposed perpendicular to the pages.