Capacitorless DRAM Using Gate-All-Around Vertical Stacking
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Solution Overview
Problem
Existing DRAM memory devices without capacitors face challenges such as noise due to coupling capacitance between the word line and body, and memory instability leading to false reading and rewriting of storage data.
Innovation Solution
A memory device utilizing a single-transistor DRAM structure without a capacitor, employing a gate-all-around (GAA) technology to stack memory cells vertically, which includes a semiconductor base material, impurity regions, gate insulating layers, and gate conductor layers to manage voltage and carrier generation for writing and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-transistor DRAM structure without capacitor is used, then device complexity is reduced and integration density is improved, but noise due to coupling capacitance between word line and body increases and memory stability deteriorates
Solution Approach 1:
The patent transitions from planar 2D transistor structure to vertical 3D GAA structure by stacking multiple channel layers vertically. This dimensional change allows the channel to extend in the vertical direction through the substrate, enabling better separation of electrical potentials and reduced coupling capacitance between word line and body, thereby improving memory stability while maintaining the capacitorless single-transistor architecture.
Solution Approach 2:
The patent introduces localized impurity regions (first and second impurity regions) at specific positions within the vertical channel structure. These impurity regions are selectively doped to create potential wells that confine carriers locally, improving memory retention and stability without requiring a capacitor. This local modification of material properties addresses the reliability issue while preserving the simplified structure.
2Productivity
If vertical stacking of memory cells is implemented using GAA technology, then integration density and processing speed are improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the vertical channel into multiple segmented layers (first channel layer, second channel layer, etc.) separated by intermediate layers. Each segment can be independently controlled by separate gate electrodes, enabling fine-grained control of carrier flow and improved processing speed. This segmentation also simplifies manufacturing by allowing modular fabrication processes for each layer.
Solution Approach 2:
The vertical GAA structure serves multiple functions simultaneously: it provides high-speed carrier transport through the vertical channel, enables dense integration through stacking, and allows independent control of multiple memory cells through separate gate electrodes. This multi-functionality achieves high productivity without proportionally increasing manufacturing complexity.
3Reliability
If impurity regions are introduced in the vertical channel, then carrier confinement and memory retention are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediate layers between the vertical channel layers, which serve as mediators during the impurity doping process. These intermediate layers can be selectively removed or modified to enable precise implantation of impurity regions at specific vertical positions. This intermediary structure facilitates accurate carrier confinement without requiring extremely high manufacturing precision for direct impurity placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise and memory instability, enabling high-density and high-speed MOS circuit operation with improved voltage margin and reduced power consumption.
Implementation Method 1
a first gate insulating layer partially covering the semiconductor base material and the first impurity region; a first gate conductor layer formed in proximity to the first impurity region and partially covering the first gate insulating layer; a second gate insulating layer partially covering the first semiconductor base material without contacting the first gate conductor layer; a second gate conductor layer partially covering the second gate insulating layer without contacting the first gate conductor layer
Data Source
AI summary
A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer is provided on one side of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a source line, a word line, and a plate line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.