Capacitor-less DRAM Gate Segmentation for Noise Reduction
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Solution Overview
Problem
Capacitive coupling between the word line and the floating body in capacitor-less single-transistor DRAMs causes direct noise transmission, leading to erroneous reading or rewriting of storage data, making it difficult to commercially introduce such DRAMs.
Innovation Solution
A memory device with a structure comprising a semiconductor base material, impurity layers, gate insulating layers, and gate conductor layers, where the gate capacitance of one gate conductor layer is larger than the other, allowing controlled page write and erase operations, and using sense amplifier circuits to read memory cell currents, reducing noise impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but noise transmission causes erroneous reading or rewriting of storage data
Solution Approach 1:
The gate structure is divided into two separate gate conductor layers (first gate conductor layer and second gate conductor layer) with different gate capacitances. This segmentation allows independent control of capacitive coupling effects, enabling the first gate to perform data writing while the second gate performs data reading with minimal noise interference.
Solution Approach 2:
Different regions of the gate structure are assigned different capacitance values to perform different functions. The first gate conductor layer has higher gate capacitance optimized for write operations, while the second gate conductor layer has lower gate capacitance optimized for read operations, allowing each part to have optimal characteristics for its specific function.
2Ease of operation
If word line voltage is changed during data reading or writing, then data operation is enabled, but direct noise transmission to floating body causes erroneous reading or rewriting
Solution Approach 1:
The second gate conductor layer acts as an intermediary between the word line and the floating body during read operations. By controlling the voltage of the second gate while maintaining the first gate at a fixed potential, the invention mediates the interaction to enable data reading without allowing direct noise transmission to the floating body, thus preventing erroneous reading or rewriting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution minimizes noise transmission during data reading and writing, enhancing data integrity and enabling the commercial viability of capacitor-less single-transistor DRAMs by reducing capacitive coupling effects.
Implementation Method 1
Capacitive coupling between the word line and the floating body in capacitor-less single-transistor DRAMs causes direct noise transmission
Implementation Method 2
accelerated electrons that flow from the source N+ layer 103 toward the drain N+ layer 104 collide with the Si lattice, and with kinetic energy lost at the time of collision, electron-positive hole pairs are generated (impact ionization phenomenon)
Data Source
AI summary
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a driving control line, and the bit lines are connected to sense amplifier circuits with a switch circuit therebetween. In a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and in a page sum-of-products read operation, a voltage is applied to the driving control line such that memory cell currents, in the group of memory cells, flowing into the bit lines multiply N-fold (N is a positive integer).