Capacitorless DRAM Gate Segmentation for Noise Reduction
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Solution Overview
Problem
Capacitorless single-transistor DRAMs face challenges due to large capacitive coupling between the word line and the floating body, leading to misreading or erroneous rewriting of storage data.
Innovation Solution
A semiconductor memory device with a dynamic flash memory cell structure that includes a semiconductor base material with a floating body, where positive hole groups generated by impact ionization or gate-induced drain leakage current are held by controlling voltages applied to various regions, allowing for controlled write, erase, and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If capacitorless single-transistor DRAM structure is used, then packaging density is improved, but capacitive coupling noise increases causing misreading or erroneous rewriting
Solution Approach 1:
The gate structure is segmented into two separate gate electrodes (first gate electrode and second gate electrode) instead of using a single gate. This segmentation allows independent control of each gate, enabling the first gate to hold positive hole groups while the second gate performs read operations, thereby reducing capacitive coupling noise between the gate and floating body during read operations.
Solution Approach 2:
The first gate electrode acts as an intermediary structure between the control circuit and the floating body. By introducing this intermediate gate that can be independently controlled, the patent mediates the interaction between the control signal and the storage node, allowing voltage control to suppress capacitive coupling effects during read operations.
2Device complexity
If single gate structure is used, then device complexity is reduced, but control precision over capacitive coupling is insufficient
Solution Approach 1:
The gate is divided into two separate gate electrodes that can be controlled independently. This segmentation provides finer control precision over the floating body voltage, allowing the system to maintain positive hole groups during write operations while suppressing capacitive coupling noise during read operations, thereby achieving the required voltage control precision.
3Speed
If high voltage is applied to word line during read operation, then read speed is improved, but capacitive coupling causes noise and potential data errors
Solution Approach 1:
The read operation uses the second gate electrode to apply high voltage to the word line for fast read speed, while the first gate electrode maintains control over the floating body to suppress capacitive coupling noise. This segmented gate control allows simultaneous achievement of high read speed and high data reading accuracy.
Solution Approach 2:
The first gate electrode serves as an intermediary that mediates between the high voltage read signal on the second gate and the floating body. By independently controlling the first gate voltage, the system can suppress capacitive coupling effects even when the second gate applies high voltage for fast reading, thereby maintaining data reading accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces capacitive coupling noise, ensuring a sufficient margin between logic 1 and logic 0 potentials, thereby enhancing the reliability and performance of capacitorless DRAMs.
Implementation Method 1
positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current
Implementation Method 2
positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current
Data Source
AI summary
A memory device uses semiconductor elements. By controlling voltages applied to plate lines, word lines, source lines, and bit lines, the memory device performs a data write operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a data erase operation of removing positive hole groups from inside the semiconductor base material. The memory device includes a block made up of memory cells, which are arrayed in a matrix. Storage data of memory cells connected with a first word line, i.e., a selected one of the word lines, in the block is read to the bit lines by applying a first voltage to the first word line, and a second voltage to a second word line adjacent to the first word line.