Capacitor-less DRAM Gate Segmentation for Noise Reduction
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face challenges due to strong capacitive coupling between the word line and the floating body, leading to noise interference and erroneous reading or rewriting of data, which hinders commercial introduction.
Innovation Solution
A semiconductor element memory device with a block of memory cells arranged in a matrix, each cell featuring a semiconductor body, impurity regions, a gate insulator layer, and gate conductor layers. The device controls voltages to retain positive holes generated by impact ionization or gate-induced drain leakage, allowing for data retention and erasure operations with reduced noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but noise interference from capacitive coupling causes erroneous reading or rewriting
Solution Approach 1:
The gate conductor layer is divided into two separate layers: a first gate conductor layer and a second gate conductor layer. This segmentation allows independent voltage control of each layer, enabling the first layer to retain positive holes while the second layer controls capacitive coupling to minimize noise interference during read operations.
Solution Approach 2:
The first gate conductor layer acts as an intermediary between the word line and the floating body. It mediates the capacitive coupling effect by being positioned between the second gate conductor layer (connected to word line) and the floating body, thus reducing direct noise coupling while still allowing controlled charge retention.
2Speed
If strong capacitive coupling between word line and floating body is present, then write speed is improved, but noise interference increases causing erroneous operation
Solution Approach 1:
The voltage applied to the first gate conductor layer is dynamically adjusted during different operation phases. During write operations, the first gate conductor layer voltage is controlled to allow strong capacitive coupling for fast writing, while during read operations, the voltage is adjusted to minimize coupling and reduce noise interference.
Solution Approach 2:
The electrical parameters (voltage levels) of the gate conductor layers are changed based on operation mode. By controlling the voltage of the first gate conductor layer differently during write versus read operations, the system optimizes both write speed and read accuracy by adjusting the strength of capacitive coupling dynamically.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces noise interference and improves data integrity, enabling reliable data storage and retrieval in capacitor-less single-transistor DRAMs, thus facilitating their commercial adoption.
Implementation Method 1
a group of positive holes generated by an impact ionization phenomenon or a gate-induced drain leakage current
Implementation Method 2
a group of positive holes generated by an impact ionization phenomenon or a gate-induced drain leakage current
Implementation Method 3
first capacitive coupling between the first gate conductor layer and the semiconductor body and second capacitive coupling between the second gate conductor layer and the semiconductor body
Data Source
AI summary
A semiconductor-element-including semiconductor memory device includes a block in which a plurality of memory cells CL00 to CL13 are arranged in a matrix, in which a data retention operation is performed in which voltages applied to plate lines PL0 and PL1, word lines WL0 and WL1, a source line SL, and bit lines BL0 to BL3 are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and a data erase operation is performed in which the voltages applied to the plate lines PL0 and PL1, the word lines WL0 and WL1, the source line SL, and the bit lines BL0 to BL3 are controlled to discharge the group of positive holes from inside the semiconductor body and the voltage of the semiconductor body is lowered with capacitive coupling with the plate lines PL0 and PL1 and capacitive coupling with the word lines WL0 and WL1. For the memory cells in the block, one or both of a memory re-write operation for the memory cells CL00, CL02, CL03, CL11, and CL13 that are in a state of the data retention operation and a memory re-erase operation for the memory cells CL01, CL10, and CL12 in a state of the data erase operation are performed for all of the memory cells in the block simultaneously.