Capacitorless DRAM Gate Segmentation for Voltage Margin
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges such as noise due to coupling capacitance between a word line and a body, memory instability leading to false readings and rewrites, and insufficient voltage margin in capacitorless DRAM cells.
Innovation Solution
A semiconductor memory device with a single-transistor DRAM configuration, featuring a MOS transistor with a unique gate structure design. This design includes a semiconductor base material, impurity regions, and distinct gate insulating and conductor layers, which control capacitance and threshold voltage to enhance memory stability and operation margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a capacitorless DRAM cell structure is used, then device integration density is improved, but voltage margin becomes insufficient due to high dependency on coupling of gate electrode from word line
Solution Approach 1:
The gate electrode is segmented into two separate gates: a first gate electrode connected to the word line and a second gate electrode connected to the bit line. This segmentation allows independent control of each gate, reducing the voltage dependency on word line coupling while maintaining the capacitorless structure for high integration density.
2Device complexity
If coupling capacitance between word line and body is present, then device structure is simplified, but noise increases
Solution Approach 1:
The harmful coupling capacitance between the word line and body is extracted and isolated by introducing a separate second gate electrode connected to the bit line. This extraction allows the word line to be electrically separated from the body, eliminating the noise source while maintaining structural simplicity.
3Adaptability or versatility
If floating body channels are used in twin-transistor memory element, then device functionality is enhanced, but operation margin between 1 and 0 at writing cannot be set sufficiently large
Solution Approach 1:
Different gate electrodes are assigned different connection characteristics: the first gate electrode connects to the word line for selection, while the second gate electrode connects to the bit line for data storage control. This local differentiation of gate connections creates distinct functional zones, enabling sufficient operation margin between logic states while maintaining enhanced device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces noise and improves memory stability by managing capacitance and threshold voltage, enabling high-density, high-speed, and robust memory operations with an expanded operation voltage margin.
Implementation Method 1
a value obtained by dividing a capacitance of a MOS gate structure constituted by the second gate conductor layer, the second gate insulating layer, and the semiconductor base material by an area of contact between the second gate conductor layer and the second gate insulating layer is different from a value obtained by dividing a capacitance of a MOS gate structure constituted by the first gate conductor layer, the first gate insulating layer, and the semiconductor base material by an area of contact between the first gate conductor layer and the first gate insulating layer
Implementation Method 2
a first impurity region connected to one end of the semiconductor base material; a second impurity region connected to another end of the semiconductor base material on a side opposite to the first impurity region
Data Source
AI summary
A p layer is a semiconductor base material. An n+ layer is disposed on one extension side of the layer. An n+ layer is disposed on the opposite side in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in electrical separation from the layer. Memory operation is performed by applying voltage to each of the layers. In this case, the gate capacitance of a MOS structure constituted by the layers per unit area is smaller than that of a MOS structure constituted by the layers.