Capacitorless DRAM Groove Structure for Noise Reduction
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Solution Overview
Problem
In single-transistor DRAMs without a capacitor, capacitive coupling between the word line and the floating body leads to noise interference, causing false reading and writing of data, which hinders practical application due to insufficient voltage margin.
Innovation Solution
A memory device with a semiconductor element featuring a groove structure and specific impurity layers, allowing for controlled voltage applications to perform memory operations through impact ionization and gate-induced drain leakage, thereby managing electron and hole generation and accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-transistor DRAM without a capacitor is used, then device integration is improved, but capacitive coupling between the word line and floating body causes noise interference and false reading/writing
Solution Approach 1:
The patent introduces a semiconductor layer with controlled carrier concentration as an intermediary between the substrate and the transistor structure. This intermediary layer acts as a buffer that reduces the capacitive coupling effect between the word line and the floating body, thereby mitigating noise interference while maintaining the capacitorless single-transistor configuration for high integration.
2Speed
If complete depletion of the substrate is achieved, then transistor performance is improved, but adverse effects on device stability increase
Solution Approach 1:
The patent changes the parameter of carrier concentration in the semiconductor layer from complete depletion to partially depleted state with controlled carrier concentration. This parameter change allows the transistor to maintain good performance while avoiding the severe adverse effects of complete substrate depletion, achieving a balance between speed and stability.
3Speed
If the groove depth is increased to improve transistor characteristics, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the parameter of groove depth from deep grooves to shallow grooves with a depth of 0.1-1.0 μm. This parameter change improves transistor characteristics while significantly reducing the manufacturing precision requirements for groove depth control, making the device more feasible for mass production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances data retention time, reduces power consumption, and expands the operational voltage margin, enabling high-speed and reliable memory operations.
Implementation Method 1
operation of generating electrons and holes in the second semiconductor layer and the second impurity layer by an impact ionization phenomenon with current flowing between the third impurity layer and the fourth impurity layer
Implementation Method 2
operation of generating electrons and holes in the second semiconductor layer and the second impurity layer by an impact ionization phenomenon with current flowing between the third impurity layer and the fourth impurity layer or by gate-induced drain leakage current
Data Source
AI summary
A groove is formed in a first semiconductor layer 1, a sidewall of the groove is coated with a first insulating film 2, a first impurity layer 3 and a second impurity layer 4 thereon are disposed in the groove, a second semiconductor layer 7 is disposed on the second impurity layer, a first semiconductor is disposed at the other part, an n+ layer 6a and an n+ layer 6c are positioned at respective ends of the second semiconductor layer 7 and connected to a source line SL and a bit line BL, respectively, a first gate insulating layer 8 is formed on the second semiconductor layer 7, and a first gate conductor layer 9 is connected to a word line WL. Voltage applied to the source line SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region 12 of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes from the channel region 12.