Capacitor-less DRAM with Ground Line Shielding
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face issues with erroneous reading or rewriting due to strong capacitive coupling between the word line and the floating body, which complicates the commercial introduction of these memory devices.
Innovation Solution
The semiconductor memory device incorporates a semiconductor base material with impurity layers and gate insulating and conductor layers, allowing for controlled voltage operations to manage electron and hole discharge, thereby performing write and erase operations while minimizing capacitive coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but capacitive coupling noise between word line and floating body causes erroneous reading or rewriting
Solution Approach 1:
A ground line is introduced as an intermediary element between the word line and the floating body. This ground line acts as a shield that intercepts and redirects capacitive coupling noise, preventing it from directly affecting the floating body potential and causing read errors.
Solution Approach 2:
The harmful capacitive coupling effect is extracted and redirected to the ground line rather than being allowed to affect the floating body. By providing a dedicated path for the noise current through the ground line, the harmful effect is separated from the sensitive memory storage node.
2Speed
If strong capacitive coupling between word line and floating body occurs, then write speed is improved, but erroneous rewriting of stored data happens
Solution Approach 1:
The ground line serves as a mediator that captures excess capacitive coupling current during write operations. By providing this intermediate path, the ground line prevents the capacitive coupling from causing erroneous rewriting of stored data while still allowing sufficient write speed.
3Device complexity
If floating body potential changes due to capacitive coupling, then operation margins are reduced, but device structure is simplified
Solution Approach 1:
The ground line acts as a stabilizing intermediary that references the floating body potential to a stable ground level. This reduces unwanted potential fluctuations caused by capacitive coupling, thereby improving operation margins while maintaining the simplified capacitor-less structure.
Solution Approach 2:
The ground line automatically compensates for potential fluctuations in the floating body by providing a reference path. This self-adjusting mechanism improves operation margins without requiring additional control circuitry or complex stabilization mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces current consumption and increases operation margins by effectively managing positive holes generated during write operations, thus enhancing the reliability and performance of capacitor-less single-transistor DRAMs.
Implementation Method 1
a memory write operation is performed by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer to perform an operation of discharging a group of electrons among the group of electrons and a group of positive holes through the first impurity layer or the second impurity layer, the group of electrons and the group of positive holes being generated inside the channel semiconductor layer in a first boundary region between the first impurity layer and the channel semiconductor layer or in a second boundary region between the second impurity layer and the channel semiconductor layer by a gate-induced drain leakage current
Data Source
AI summary
On a substrate Sub, a semiconductor base material (Si pillar) that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction a first impurity layer and a second impurity layer that are disposed on respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer that surround the semiconductor base material between the first impurity layer and the second impurity layer, and a channel semiconductor layer are disposed. Voltages are applied to perform a memory write operation of discharging a group of electrons from the channel semiconductor layer and retaining some of a group of positive holes in the channel semiconductor layer generated inside the channel semiconductor layer by a gate-induced drain leakage current, and a memory erase operation of discharging the group of positive holes retained in the channel semiconductor layer.