Capacitor-less DRAM Impact Ionization Write Mechanism
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Solution Overview
Problem
Capacitor-less single-transistor DRAM memory devices face challenges in providing a sufficient margin between '1' and '0' potentials due to strong capacitive coupling between the word line and the floating body, leading to erroneous reading or writing of storage data.
Innovation Solution
A semiconductor memory device with a vertical or horizontal semiconductor base material, impurity layers, gate insulating layers, and gate conductor layers, where voltages are controlled to perform impact ionization and discharge operations, reducing capacitive coupling noise and enhancing the potential difference margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitor-less single-transistor DRAM memory device is used, then device complexity is reduced and integration density is improved, but capacitive coupling noise between word line and floating body increases causing insufficient potential difference margin
Solution Approach 1:
The patent introduces a tunnel insulating layer as an intermediary between the word line and the floating body. This tunnel insulating layer acts as a mediator that blocks direct capacitive coupling while allowing controlled charge transfer through tunneling effects, thereby reducing noise interference and ensuring reliable data operations in the simplified capacitor-less structure.
2Speed
If strong capacitive coupling exists between word line and floating body, then write speed is improved, but potential difference margin between '1' and '0' states decreases leading to erroneous reading
Solution Approach 1:
The patent modifies the electrical parameters of the interface between word line and floating body by introducing the tunnel insulating layer. This changes the coupling mechanism from direct strong capacitive coupling to controlled quantum tunneling, adjusting the effective capacitance and charge transfer characteristics to achieve both fast writing and reliable reading with sufficient potential difference margin.
3Ease of manufacture
If capacitor-less single-transistor structure is adopted, then manufacturing process is simplified, but noise from capacitive coupling causes data integrity issues
Solution Approach 1:
The tunnel insulating layer serves as a protective intermediary that blocks harmful capacitive coupling noise while maintaining the simplified capacitor-less single-transistor structure. This intermediary layer preserves the manufacturing advantages while eliminating the data integrity issues caused by direct capacitive coupling between the word line and floating body.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces capacitive coupling noise, improving data integrity and enabling the commercial introduction of capacitor-less single-transistor DRAM memory devices by maintaining a sufficient potential difference between '1' and '0' states.
Implementation Method 1
perform an operation of causing an impact ionization phenomenon to occur in a first boundary region between the first channel semiconductor layer and the second channel semiconductor layer, a second boundary region between the first impurity layer and the first channel semiconductor layer, or a third boundary region between the second impurity layer and the second channel semiconductor layer by a current that flows between the first impurity layer and the second impurity layer
Data Source
AI summary
A semiconductor base material stands on a substrate in a vertical direction or extends in a horizontal direction. Between first and second impurity layers disposed at the ends of the semiconductor base material, first and second gate insulating layers and first and second gate conductor layers are disposed around the semiconductor base material. A memory write operation is performed where voltages are applied to the first and second impurity layers and the first and second gate conductor layers to cause an impact ionization phenomenon to occur in a channel region, and among generated groups of electrons and positive holes, the group of electrons are discharged from the channel region and some of the group of positive holes are retained in the channel region. A memory erase operation is performed where the retained group of positive holes are discharged via any of or both of the first and second impurity layers.