Capacitorless DRAM Noise Reduction via Charge Pump Mediator
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Solution Overview
Problem
Capacitorless single-transistor DRAMs experience strong capacitive coupling between the word line and the floating body, leading to noise transmission during data reading or writing, resulting in erroneous readings and rewrites, which hinders practical implementation.
Innovation Solution
The memory apparatus incorporates a dynamic flash memory cell structure with a semiconductor base material standing upright or horizontally, featuring a first and second impurity region, gate insulating layers, and gate conductor layers. Voltage control is implemented to retain or pull out holes generated through impact ionization or gate-induced drain leakage, optimizing data holding voltages during page write and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitorless single-transistor DRAM structure is used, then device integration density is improved, but capacitive coupling noise between word line and floating body increases causing erroneous readings
Solution Approach 1:
A charge pump circuit is introduced as an intermediary component between the word line and the floating body. The charge pump actively compensates for capacitive coupling noise by injecting or removing charges from the floating body in response to detected noise levels, thereby isolating the floating body from direct noise transmission while maintaining the capacitorless single-transistor structure's high integration density
2Device complexity
If strong capacitive coupling exists between word line and floating body, then device structure is simplified, but data integrity deteriorates due to noise transmission during reading
Solution Approach 1:
A feedback mechanism is implemented where the noise detection circuit continuously monitors the floating body for capacitive coupling noise, and the charge pump circuit responds by adjusting the charge state of the floating body. This closed-loop feedback system maintains data integrity by actively counteracting noise effects while preserving the simplified capacitorless single-transistor device structure
3Ease of manufacture
If capacitorless single-transistor DRAM is used, then manufacturing process is simplified, but operational reliability decreases due to erroneous rewriting
Solution Approach 1:
The charge pump circuit serves as a mediator that prevents erroneous rewriting by compensating for capacitive coupling noise during write operations. This additional component is integrated into the existing manufacturing process flow and does not require fundamentally new fabrication techniques, thus maintaining ease of manufacture while significantly improving operational reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitive coupling noise, providing a sufficient margin for the potential difference between written '1' and '0' states, thus enhancing data integrity and enabling the practical use of capacitorless single-transistor DRAMs.
Implementation Method 1
holes generated through an impact ionization phenomenon
Implementation Method 2
using a gate induced drain leakage current
Data Source
AI summary
A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and to input page data for the page write operation to a sense amplifier circuit during the page erase operation.