Capacitor-less Single-Transistor DRAM Noise Reduction
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face challenges due to strong capacitive coupling between the word line and floating body, leading to noise during data reading or writing, and gate-induced drain leakage currents that corrupt storage data, making it difficult to commercially introduce these memory devices.
Innovation Solution
A memory device with a structure comprising a semiconductor base material, impurity layers, gate insulating layers, and gate conductor layers, where the first gate conductor layer has a larger capacitance than the second, allowing controlled voltage applications to retain and discharge positive holes, and a selected driving control line is set to zero volts to isolate the driving circuit, reducing capacitive coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but capacitive coupling noise between word line and floating body increases
Solution Approach 1:
A plate line is introduced as an intermediary element between the word line and the floating body. The plate line acts as a mediator that reduces the direct capacitive coupling between the word line and floating body, thereby reducing noise while maintaining the capacitor-less single-transistor structure for high integration density
2Ease of operation
If strong capacitive coupling between word line and floating body exists, then data write operation is simplified, but noise during data reading or writing increases
Solution Approach 1:
The gate control is segmented into two independent gates: the word line gate and the plate line gate. This segmentation allows independent control of the two gates, enabling simplified data write operation through voltage application to one gate while reducing noise during read operations through coordinated control of both gates
3Device complexity
If capacitor-less single-transistor DRAM is implemented, then device complexity is reduced, but gate-induced drain leakage current increases
Solution Approach 1:
The plate line serves as an intermediary that modulates the electric field distribution in the channel. By controlling the plate line voltage, the electric field at the drain junction can be reduced, thereby suppressing gate-induced drain leakage current while maintaining the simple capacitor-less single-transistor device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise during data operations, enhances data retention, and prevents data corruption, making it feasible to commercially introduce capacitor-less single-transistor DRAMs with improved reliability and performance.
Implementation Method 1
capacitive coupling between the first gate conductor layer and the channel semiconductor layer and capacitive coupling between the second gate conductor layer and the channel semiconductor layer
Implementation Method 2
generated by an impact ionization phenomenon
Implementation Method 3
retaining a group of positive holes, inside the channel semiconductor layer
Data Source
AI summary
A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.