Capacitor-less DRAM Pillar Segmentation for Noise Reduction
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Solution Overview
Problem
Capacitor-less single-transistor DRAM memory cells face challenges due to significant capacitive coupling between the word line and the floating body, leading to noise and errors during read and write operations, limiting their practical use and density.
Innovation Solution
A semiconductor memory device manufacturing method that controls voltages applied to specific gate conductor layers and impurity layers to manage holes or electrons generated by impact ionization, including steps for stacking layers, forming semiconductor pillars, and oxidizing surfaces to create gate insulating layers, allowing for controlled data retention and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor-less single-transistor DRAM memory cells are used to increase integration density, then device density is improved, but capacitive coupling noise between word line and floating body increases causing read/write errors
Solution Approach 1:
The gate conductor layer is divided into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can be independently controlled. This segmentation allows selective application of voltages to different gate regions, enabling precise control of the electric field distribution and reducing unwanted capacitive coupling effects on the floating body while maintaining high device density.
Solution Approach 2:
Different voltage conditions are applied to different regions of the gate conductor layer. During write operations, specific gate electrodes receive high voltages to generate impact ionization in localized regions, while other gates maintain lower voltages to minimize noise coupling. This local quality control enables selective charge generation and reduces overall capacitive coupling noise.
2Productivity
If high voltages are applied to generate impact ionization for data writing, then data write capability is improved, but noise and errors during read operations increase
Solution Approach 1:
The gate electrode voltages are dynamically adjusted based on the operation mode. During write operations, high voltages (e.g., 5V or higher) are applied to specific gate electrodes to generate impact ionization. During read operations, all gate electrodes are maintained at lower voltages (e.g., 0V to 2V) to minimize noise and prevent additional charge generation, thus ensuring read accuracy while maintaining write capability.
Solution Approach 2:
The memory device operates in periodic cycles alternating between write mode (high voltage application for impact ionization) and read mode (low voltage application for noise-free sensing). This periodic switching of voltage conditions allows the system to achieve both strong write capability and reliable read accuracy by ensuring that high-voltage effects are only present during write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitive coupling noise, enhances the operational margin between '1' and '0' states, and increases the density and performance of DRAM memory cells, making them more suitable for practical use.
Implementation Method 1
a data retention operation in which voltages to be applied to a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, a first impurity layer, and a second impurity layer are controlled to retain, inside a semiconductor pillar, a group of holes or electrons that are generated by an impact ionization phenomenon
Implementation Method 2
Capacitor-less single-transistor DRAM memory cells face challenges due to significant capacitive coupling between the word line and the floating body, leading to noise and errors during read and write operations
Implementation Method 3
a step of oxidizing an outermost surface of the semiconductor pillar exposed in the second hole to form a first gate insulating layer, oxidizing an outermost surface of the semiconductor pillar exposed in the third hole to form a second gate insulating layer, and oxidizing an outermost surface of the semiconductor pillar exposed in the fourth hole to form a third gate insulating layer
Data Source
AI summary
A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.