Capacitorless DRAM Pillar Segmentation for Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Capacitorless single-transistor DRAM memory devices face issues with erroneous reading and writing due to large capacitive coupling between the word line and the floating body, leading to insufficient potential difference margins and challenges in achieving high-density and high-performance memory cells.
Innovation Solution
The memory device employs a vertical semiconductor pillar structure with specific impurity layers and gate insulating and conductor layers, controlling voltages to form hole or electron groups through impact ionization or gate-induced drain leakage, and managing these groups for data write and erase operations, while optimizing gate capacitances to reduce noise and improve operational margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitorless single-transistor DRAM memory cell is used, then device complexity is reduced and integration density is improved, but capacitive coupling between word line and floating body causes noise and erroneous reading/writing
Solution Approach 1:
The patent divides the single transistor into two separate transistors (first transistor for writing, second transistor for reading) with distinct gate lines (first word line and second word line). This segmentation isolates the write and read operations, preventing capacitive coupling noise from affecting both operations simultaneously and eliminating erroneous reading/writing while maintaining integration density.
Solution Approach 2:
The patent introduces a coupling capacitor as an intermediary element between the floating body and the second word line. This capacitor mediates the capacitive coupling effect, allowing controlled signal transmission during read operations while blocking noise during write operations, thereby improving data reading and writing accuracy.
2Quantity of substance
If vertical semiconductor pillar structure is used, then memory density is improved, but noise from word line oscillation directly affects floating body
Solution Approach 1:
The patent segments the word line function into two separate word lines (first and second) that are spatially and functionally separated. The first word line is positioned away from the vertical semiconductor pillar during write operations, while the second word line is positioned closer during read operations. This segmentation reduces noise from word line oscillation affecting the floating body while maintaining high memory density through vertical structure.
Solution Approach 2:
The coupling capacitor serves as an intermediary that filters and controls the interaction between the second word line and the floating body. It allows beneficial capacitive coupling during read operations while attenuating noise from word line oscillation, thereby reducing harmful factors while preserving the vertical pillar structure for high density.
3Productivity
If large capacitive coupling between word line and floating body is present, then write operation efficiency is improved, but potential difference margin becomes insufficient
Solution Approach 1:
The patent segments the word line into two distinct lines with different positioning strategies. The first word line is positioned away from the floating body during write operations to reduce unwanted capacitive coupling, while the second word line is positioned closer during read operations to enhance signal detection. This segmentation maintains write operation efficiency while ensuring sufficient potential difference margin.
Solution Approach 2:
The patent dynamically changes the positioning and activation of word lines based on the operation mode. During write operations, the first word line is activated with specific voltage patterns; during read operations, the second word line is activated with different voltage patterns. This dynamic approach optimizes both write efficiency and potential difference margin by adapting capacitive coupling conditions to operational requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data integrity by minimizing noise-induced errors and allows for higher integration and performance in dynamic flash memory, achieving a stable potential difference and increased memory density.
Implementation Method 1
forming a hole group or an electron group serving as majority carriers of the first semiconductor layer and the second semiconductor layer, the hole group or the electron group being formed by an impact ionization phenomenon
Implementation Method 2
the hole group or the electron group being formed by an impact ionization phenomenon or a gate induced drain leakage current
Data Source
AI summary
A first dynamic flash memory cell formed on a first Si pillar 25a including an N+ layer 21a, a P layer 22a, and an N+ layer 21b, and a second dynamic flash memory cell formed on a second Si pillar 25b including a P layer 22b and an N+ layer 21c, the first dynamic flash memory cell and the second dynamic flash memory cell sharing the N+ layer 21b that is connected to a first bit line BL1, are stacked on top of one another on a P-layer substrate 20 to form a dynamic flash memory. In plan view, a first plate line PL1, a first word line WL1, a second word line WL2, and a second plate line PL2 extend in the same direction and are formed to be perpendicular to a direction in which the first bit line BL1 extends.