Capacitor-less DRAM Using Plate Line to Suppress Leakage
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Solution Overview
Problem
Capacitor-less single-transistor DRAMs face challenges due to strong capacitive coupling between the word line and floating body, leading to noise during data reading/writing, and gate-induced drain leakage currents that corrupt storage data, making it difficult to commercially introduce these memory devices.
Innovation Solution
A semiconductor memory device with a structure comprising a semiconductor base material, impurity layers, gate insulating and conductor layers, and a channel semiconductor layer, where voltages are controlled to retain or discharge positive holes generated by impact ionization, and specific voltage applications during write, erase, and read operations minimize capacitive coupling and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but noise due to strong capacitive coupling between word line and floating body increases
Solution Approach 1:
A plate line is introduced as an intermediary element between the word line and the floating body. The plate line acts as a mediator to control and reduce the capacitive coupling between the word line and floating body, thereby reducing noise during read/write operations while maintaining the capacitor-less single-transistor structure for high integration density
2Area of moving object
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but gate-induced drain leakage current increases causing data corruption
Solution Approach 1:
The plate line serves as a mediator to control the voltage distribution in the memory cell. By properly controlling the plate line voltage during write and read operations, the gate-induced drain leakage current is suppressed, preventing data corruption while maintaining the high integration density benefits of the capacitor-less single-transistor structure
Solution Approach 2:
The invention changes the voltage parameters applied to different lines (word line, bit line, plate line) during different operations. By dynamically adjusting these voltage parameters, the gate-induced drain leakage current is controlled and minimized, ensuring data retention reliability while maintaining device integration density
3Reliability
If non-selected word line is set to negative voltage to improve retention, then data retention is improved, but gate-induced drain leakage current increases corrupting storage data
Solution Approach 1:
Instead of directly setting the non-selected word line to negative voltage (which causes GIDL current), the plate line is used as an intermediary to control the voltage distribution. The plate line voltage is adjusted to achieve proper data retention while suppressing the gate-induced drain leakage current that would otherwise corrupt storage data
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces noise and leakage currents, enhancing data retention and reliability, allowing for the commercial introduction of capacitor-less single-transistor DRAMs with improved performance and stability.
Implementation Method 1
voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to retain a group of positive holes, inside the channel semiconductor layer, generated by an impact ionization phenomenon
Data Source
AI summary
A memory device includes pages each constituted by memory cells, and a page write operation of retaining a group of positive holes, inside a channel semiconductor layer, generated by an impact ionization phenomenon by controlling voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell and a page erase operation of discharging the group of positive holes by controlling the voltages are performed. The first and second impurity layers and the first and second gate conductor layers of each memory cell is connected to a source line, a bit line connected to a sense amplifier circuit, a word line, and a driving control line respectively. In a page read operation, page data in a selected page is read to the bit lines. To the driving control line connected to a non-selected page, a voltage of zero volt or lower is applied.