Capacitorless DRAM Memory Cell Voltage Control for Read Stability
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Solution Overview
Problem
Capacitorless single-transistor DRAM memory cells face issues with large capacitive coupling between the word line and floating body, leading to potential noise and misreading or erroneous rewriting during data read or write operations, making them difficult to implement commercially.
Innovation Solution
A semiconductor memory cell design with a first and second impurity well layer, semiconductor base material, and separate gate conductor layers, where positive hole groups are controlled by applied voltages to perform memory write and erase operations, and a logical-physical conversion table is used to manage the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If capacitorless single-transistor DRAM memory cell is used, then packaging density is improved, but capacitive coupling noise between word line and floating body increases causing misreading or erroneous rewriting
Solution Approach 1:
A charge pump circuit is introduced as an intermediary mechanism to actively control and regulate the voltage potential of the floating body. This charge pump compensates for capacitive coupling effects by dynamically adjusting charge levels, thereby preventing noise-induced misreading or erroneous rewriting while maintaining the compact capacitorless structure.
Solution Approach 2:
The invention dynamically changes the voltage parameter of the floating body through controlled charge pumping. By actively modulating the floating body voltage in response to operational states, the system compensates for capacitive coupling variations and maintains stable logic state differentiation despite the compact design.
2Measurement precision
If floating body voltage is increased to improve logic state differentiation, then measurement precision is improved, but risk of erroneous rewriting due to capacitive coupling increases
Solution Approach 1:
A feedback control mechanism is implemented where the charge pump circuit continuously monitors and adjusts the floating body voltage based on the detected logic state. This feedback loop ensures that voltage levels are optimized for differentiation while preventing excessive voltage that could cause erroneous rewriting through capacitive coupling to the word line.
Solution Approach 2:
The floating body voltage is made dynamic rather than static, allowing real-time adjustment based on operational conditions. The charge pump actively modulates voltage levels during read and write operations, enabling optimal differentiation during reading while preventing over-voltage conditions that would cause erroneous rewriting.
3Device complexity
If compact memory cell structure is used, then device complexity is reduced, but capacitive coupling effects are amplified
Solution Approach 1:
The charge pump circuit serves as an intermediary control mechanism that decouples the direct capacitive interaction between word line and floating body. By introducing this active control element, the system can maintain compact geometry while the charge pump compensates for coupling effects through dynamic charge regulation.
Solution Approach 2:
The invention changes the electrical parameters (voltage and charge levels) of the floating body dynamically to compensate for capacitive coupling effects. This parameter modulation allows the compact structure to function reliably by actively adjusting operating conditions to counteract coupling-induced noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design minimizes capacitive coupling noise, ensuring stable potential differences between logic states, reducing misreading and erroneous rewriting, and enabling efficient memory operations.
Implementation Method 1
Field Effect-Controlled Charge Regeneration
Implementation Method 2
positive hole groups generated by an impact ionization phenomenon
Implementation Method 3
positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current
Data Source
AI summary
By controlling voltages applied to plate lines, word lines, source lines, and bit lines, a memory device that uses semiconductor elements performs a data retention operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a memory erase operation of removing positive hole groups from inside the semiconductor base material. The memory device also performs a data erase operation during the memory erase operation to remove positive hole groups from inside the semiconductor base material of all the memory cells in a block made up of the memory cells, which are arrayed in a matrix.