Capacitorless Semiconductor Memory with Vertical Charge Trap Structure
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Solution Overview
Problem
The challenge is to develop a semiconductor memory device with high integration and performance that does not rely on capacitors, as they limit the miniaturization and functionality of DRAM due to difficulties in reducing capacitor size.
Innovation Solution
A capacitorless semiconductor memory device is designed with a semiconductor substrate, vertical gate structure, charge trap layers, and semiconductor patterns with specific doping and insulation layers, allowing for high integration and scalability by using a tunnel field effect transistor (TFET) mechanism to store data without capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used in DRAM to store data, then data storage function is achieved, but device integration density is limited due to the large area required for capacitors
Solution Approach 1:
The patent removes the capacitor component entirely from the memory cell structure, replacing the conventional capacitor-based storage mechanism with a transistor-based charge trap mechanism. This extraction of the capacitor eliminates the primary area-consuming element while maintaining data storage functionality through alternative physical mechanisms in the TFET structure.
Solution Approach 2:
The patent substitutes the electrical charge storage mechanism (capacitor) with a quantum mechanical tunneling mechanism (TFET). The tunnel field effect transistor uses band-to-band tunneling to trap and release charges in the channel region, replacing the electrostatic field storage of conventional capacitors with a quantum mechanical effect that achieves similar functionality in a smaller footprint.
2Area of stationary object
If capacitor size is reduced to increase integration density, then device integration is improved, but capacitor performance and reliability deteriorate
Solution Approach 1:
By completely removing the capacitor from the memory cell architecture, the patent eliminates the trade-off between capacitor size and performance. The charge trap mechanism in the TFET channel provides sufficient charge storage capacity without requiring a separate capacitor component, thereby avoiding the performance degradation that would result from miniaturizing conventional capacitors.
3Quantity of substance
If more capacitors are added to increase memory capacity, then memory capacity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the storage function traditionally performed by a separate capacitor into the transistor structure itself. The TFET channel region serves dual purposes: as the conduction path for transistor operation and as the charge trap region for data storage. This merging eliminates the need for separate capacitor components and their associated word lines and bit lines, thereby reducing device complexity while increasing capacity.
Solution Approach 2:
The TFET structure performs multiple functions within a single component: it acts as the selection transistor for row decoding, provides the charge trap mechanism for data storage, and enables column decoding through its tunneling characteristics. This multi-functionality reduces the overall number of components needed per memory bit, simplifying the device structure and manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables significant increase in erase speed and high performance with high integration and scalability, enhancing competitiveness and reliability of the memory device.
Implementation Method 1
a plurality of charge trap layers each having a horizontal cross-section with a first ring shape surrounding the gate structure
Implementation Method 2
The source region may be doped with a first conductivity type impurity. The drain region may be doped with a second conductivity type impurity.
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.