Capacitor-less Memory with Double PN Junctions
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Solution Overview
Problem
Existing Dynamic Random Access Memory (DRAM) devices face challenges in reducing memory cell size and achieving high integrity due to the need for high aspect ratio capacitors, which increase process complexity and cost, and are prone to 'disturbance' voltages affecting adjacent cells, while Schottky junction-based memory devices are limited by metal electrode selection and interface defects.
Innovation Solution
A memory device with a double PN junction structure, featuring a Schottky junction between the semiconductor layer and the anode and an Ohmic junction between the semiconductor layer and the cathode, allowing for a capacitor-less design with improved reliability and reduced size, using an NPN or PNP-type semiconductor layer with varying concentration N-type layers to control the potential barrier and prevent direct metal-semiconductor contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a high aspect ratio capacitor is used to reduce memory cell size, then storage capacity increases, but process complexity and reliability deteriorate
Solution Approach 1:
The patent extracts and eliminates the capacitor component from the traditional 1T-1C DRAM structure, replacing it with a capacitor-less memory device that uses a single transistor with a specially designed substrate structure to store charge, thereby simplifying the device structure and reducing process complexity
Solution Approach 2:
The patent employs a composite substrate structure consisting of a first substrate, a second substrate, and an intermediate layer, where the intermediate layer includes a first region with different electrical characteristics than a second region, creating a complex material system that enables capacitor-less operation while maintaining storage functionality
2Quantity of substance
If a high aspect ratio capacitor is used to reduce memory cell size, then storage capacity increases, but stability and reliability worsen
Solution Approach 1:
By removing the high aspect ratio capacitor from the structure, the patent eliminates the source of instability and reliability problems associated with such capacitors, while maintaining storage capacity through the alternative substrate-based charge storage mechanism
3Volume of moving object
If a 2-terminal TRAM is used to reduce device size, then memory device size decreases, but disturbance to adjacent cells increases
Solution Approach 1:
The patent introduces a control gate as an intermediary element that mediates the operation of the memory device, allowing selective control of charge storage and retrieval processes to prevent disturbance to adjacent cells while maintaining small device size
Solution Approach 2:
The patent implements dynamic control through the control gate, which can be adjusted to different voltage states to selectively enable or disable charge storage in the substrate, providing temporal and spatial control that prevents disturbance to adjacent memory cells
4Device complexity
If a Schottky junction-based memory device is used to simplify structure, then device complexity decreases, but material selection limitations increase
Solution Approach 1:
The patent extracts and removes the Schottky junction component from the device structure, replacing it with a fully semiconductor-based structure that uses the substrate and intermediate layer to achieve the desired electrical characteristics, thereby eliminating material selection limitations
Solution Approach 2:
The patent creates a composite semiconductor structure with a first substrate, second substrate, and intermediate layer having different electrical characteristics, which together provide the functionality previously requiring Schottky junctions, enabling greater material versatility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability and integrity of the memory device by controlling carrier accumulation through a control gate, reducing the reliance on specific metal electrode materials and avoiding high electric fields, thus improving operational performance and data protection in memory arrays.
Implementation Method 1
a junction between the semiconductor layer and the anode is a Schottky junction
Implementation Method 2
controlling carrier accumulation through a control gate
Implementation Method 3
double PN junction structure... allowing for a capacitor-less design
Implementation Method 4
a junction between the semiconductor layer and the cathode is an Ohmic junction
Data Source
AI summary
A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.