Capacitorless Memory via Multi-Gate Hysteresis
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Solution Overview
Problem
Conventional MOS devices face challenges in scaling due to short-channel effects and leakage current, particularly as device dimensions approach atomic thickness, leading to difficulties in completely turning off transistors and high power consumption, with existing solutions requiring high bias voltages and advanced gate dielectric materials.
Innovation Solution
A method for operating multi-gate MOS transistors with a hysteresis window is employed, allowing for a subthreshold swing of less than 60mV/decade by applying voltages to both gate electrodes with opposite signs, reducing the need for high-k gate dielectric materials and enabling low drain voltage operation, while maintaining high retention times and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the gate dielectric layer is reduced to enhance gate control, then the control of the channel is improved, but the leakage current increases due to quantum-mechanical tunneling
Solution Approach 1:
The patent employs a composite gate dielectric structure comprising multiple layers with different dielectric constants. A high-k dielectric layer is positioned adjacent to the channel region to enhance gate control, while a low-k dielectric layer is positioned adjacent to the gate electrode to reduce leakage current through quantum-mechanical tunneling. This composite structure allows simultaneous optimization of both gate control and leakage suppression.
2Length of moving object
If the channel length is reduced to enable device scaling, then the device dimensions are improved, but short-channel effects and leakage current increase
Solution Approach 1:
The patent transitions from conventional planar gate control to three-dimensional gate control by implementing a multi-layer gate dielectric structure that extends control into the vertical dimension. The stacked dielectric layers with varying dielectric constants create a graded control profile through the channel thickness, enabling effective short-channel effect suppression in scaled devices without requiring further channel length reduction.
3Reliability
If advanced gate dielectric materials with higher dielectric constant are used to reduce gate oxide thickness, then the gate control is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the gate dielectric into multiple discrete layers, each with specific dielectric constant characteristics. The first dielectric layer (high-k) provides enhanced gate control, while the second dielectric layer (low-k) mitigates leakage. This segmentation allows each layer to be optimized independently for its specific function, simplifying the overall manufacturing process compared to finding a single material that simultaneously satisfies both high control and low leakage requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of logic and memory applications on the same chip without additional cost, achieving a subthreshold swing of less than 60mV/decade, reducing power consumption, and improving scalability with low drain voltage operation.
Implementation Method 1
The first gate electrode and the semiconductor body form a first capacitively coupled contact, wherein the second gate electrode and the semiconductor body form a second capacitively coupled contact
Implementation Method 2
a semiconductor device with a hysteresis window in a characteristic of drain current versus front gate voltage
Data Source
Figure 1~3
Figure 4A~4B
Figure 5A~5B
AI summary
A capacitorless memory device based on a multi-gate MOSFET and requiring relatively low bias voltages. By providing a sufficient body factor and inducing a VT-feedback loop, using an accumulation layer to link threshold voltage with gate-to-body voltage, a hysteresis window (H) can be induced allowing the MOSFET to store '1' or '0' values (54, 51), and to read (within a program window PW) and hold (50) the stored values. The device operates with relatively low operating voltages such as 1.5V, high reliability e.g. 1016 operations, and long retention time such as ~5sec.