Capacitorless Memory Cell Layout for Data Retention and Noise Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to develop a semiconductor device with high integration density, capable of operating at high speed, retaining data for a long time, and reducing power consumption, while minimizing the impact of operation noise and data retention time issues associated with small or no storage capacitors in oxide semiconductor transistors.
Innovation Solution
A memory device design incorporating a plurality of memory cells, each comprising two transistors where one transistor's source or drain is connected to the other transistor's gate through a node, eliminating the need for a storage capacitor, and utilizing a low dielectric constant region outside the memory cell to reduce parasitic capacitance and noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a storage capacitor is reduced or eliminated in oxide semiconductor transistor memory, then integration density is improved, but data retention time is reduced and noise susceptibility increases
Solution Approach 1:
The invention extracts and eliminates the storage capacitor component from the memory cell structure by utilizing the gate capacitance of the second transistor. This removes the need for a separate capacitor while maintaining data retention functionality, directly resolving the contradiction between integration density and data retention.
Solution Approach 2:
The gate of the second transistor serves dual functions: as the control terminal for transistor operation and as the storage node for data retention. This multi-functionality eliminates the need for a dedicated storage capacitor, improving integration density while preserving data retention capability.
2Area of moving object
If transistor size is reduced for high integration, then device density is improved, but operation speed is reduced
Solution Approach 1:
The invention changes the electrical parameters of the transistors by using oxide semiconductor materials with high mobility characteristics. This allows smaller transistor dimensions to achieve the same or better operation speed compared to larger conventional transistors, resolving the density-speed tradeoff.
3Area of moving object
If oxide semiconductor transistor is used to eliminate storage capacitor, then integration density is improved, but susceptibility to operation noise increases
Solution Approach 1:
The invention introduces a low dielectric constant region as an intermediary element between memory cells. This region acts as a noise isolation barrier, blocking operation noise from affecting the memory cells while allowing the compact capacitorless structure to maintain high integration density.
Data Source
AI summary
A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.