Capacitorless Memory Device Valence Band Energy Control
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Solution Overview
Problem
Conventional capacitor-based memory devices face challenges in reducing design rule sizes, leading to increased capacitor height, aspect ratio issues, and electrical connections between adjacent capacitors, making it difficult to integrate more unit cells on a smaller area without degrading data storage capability.
Innovation Solution
A capacitorless memory device is developed, where a storage region with a different valence band energy is disposed under the channel region to trap charges, eliminating the need for a conventional capacitor and enhancing charge retention time by controlling valence band energy based on a vacuum level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of the capacitor is reduced to increase integration density, then the integration area increases, but the capacitance decreases and the capacitor height must be increased
Solution Approach 1:
The patent extracts the charge storage function from the conventional capacitor structure and relocates it to the silicon body of the transistor. By removing the separate capacitor component and using the transistor's silicon body as the charge storage region, the design eliminates the need to increase capacitor height while maintaining charge storage capability.
Solution Approach 2:
The patent merges the transistor and capacitor functions into a single integrated structure. The silicon body of the transistor serves dual purposes: as the active transistor region and as the charge storage capacitor. This consolidation eliminates the need for separate capacitor structures and their associated height constraints.
2Quantity of substance
If the capacitor height is increased to maintain capacitance, then the capacitance is maintained, but the aspect ratio increases and efficient patterning is precluded
Solution Approach 1:
The patent removes the need for high-aspect-ratio capacitor structures by extracting the charge storage function to the silicon body. This eliminates the manufacturing and patterning difficulties associated with forming tall, narrow capacitor holes.
3Quantity of substance
If the interval between adjacent capacitors is reduced to increase integration, then the integration density increases, but the capacitors collapse and may be electrically connected
Solution Approach 1:
By merging the capacitor function into the transistor's silicon body, the patent eliminates separate capacitor structures that would require spacing. The transistor structures themselves provide natural isolation, allowing tighter integration without collapse or electrical connection risks.
4Quantity of substance
If holes are accumulated in the silicon body for charge storage, then the data storage capability is achieved, but the holes leak to source and drain regions over time
Solution Approach 1:
The patent applies local quality by creating a potential well in specific regions of the silicon body using tailored doping profiles. This localized potential modulation confines holes to specific storage regions while preventing leakage to source and drain, enhancing charge retention through spatially differentiated electrical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves data storage capability and reliability by increasing charge retention time and reducing dependence on back bias, allowing for more efficient multi-level drive operations and multi-bit operations without the limitations of capacitor-based designs.
Implementation Method 1
A storage region with a different valence band energy from the channel region is disposed under the channel region
Implementation Method 2
when a higher voltage is applied to a drain of the transistor than a gate thereof, impact ionization occurs due to a strong electrical field applied to the drain of the transistor
Data Source
Figure 1~2
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Figure 5~6
AI summary
Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain electrodes connected to the channel region and disposed at both sides of the gate electrode. A storage region unit having different valence band energy from a channel region unit is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.