Capacitorless Memory Cell Vertical Stacking Integration
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Solution Overview
Problem
The challenge is to develop a memory device with higher integration capacity without relying on capacitors, as reducing capacitor size affects memory function in dynamic random access memory (DRAM) devices.
Innovation Solution
A capacitorless memory device is designed with each memory cell comprising two transistors: a read transistor and a write transistor, where the write transistor's source layer functions as the read transistor's gate, and both are vertically stacked on a substrate with specific impurity layers and barrier layers to enhance integration and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor size is reduced to increase integration capacity, then integration density is improved, but memory function deteriorates
Solution Approach 1:
The patent removes the capacitor component from the memory cell structure entirely, extracting the energy storage function to a separate write transistor mechanism. This eliminates the need to reduce capacitor size while achieving high integration density through the capacitorless 1T1C (one transistor, one capacitor-equivalent) cell design.
Solution Approach 2:
The patent replaces the physical capacitor structure with an alternative charge storage mechanism using transistor gate characteristics and impurity layer configurations. The electrical charge is stored through the interaction between the write transistor's source layer and the read transistor's impurity layers, substituting the mechanical capacitor structure with a field-effect-based storage mechanism.
2Area of stationary object
If vertical stacking is used to increase integration, then area is reduced, but short channel effects increase
Solution Approach 1:
The patent transitions from planar transistor layout to vertical stacking architecture, moving the channel structure into the third dimension. The read and write transistors are stacked vertically with shared impurity layers, reducing the lateral footprint while maintaining sufficient channel length to minimize short channel effects through the vertical channel orientation.
Solution Approach 2:
The patent implements nested transistor structures where the read transistor and write transistor share common impurity layers and substrate regions. The write transistor's source layer serves dual functions as both the write transistor's source and the read transistor's gate, creating a compact nested configuration that reduces area while controlling channel dimensions to mitigate short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for higher integration density without the need for capacitors, preventing short channel effects and enabling efficient memory operation, thus overcoming the limitations of traditional DRAM designs.
Implementation Method 1
The source layer and the body layer may form a first Schottky contact. The drain layer and the body layer may form a second Schottky contact.
Data Source
AI summary
According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.