Capacitor-Less Regulator Slew Control for Power-Up Overshoot
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Solution Overview
Problem
Capacitor-less linear regulator circuits face challenges in load stability and transient response due to the absence of external capacitors, leading to power-up overstress and voltage overshoot, which can degrade circuit performance and increase board costs.
Innovation Solution
A slew-rate control circuit is coupled to the gate node of the output transistor to control the voltage rise during power-up, and an output voltage level detection circuit is used to disable the slew control when the output voltage reaches a pre-set level, preventing output voltage overshoot. This solution includes a switch transistor and a diode-connected transistor forming a current mirror, with the diode-connected transistor having its gate node coupled to the gate node of the output transistor, and an output voltage level detection circuit that turns off the switch transistor when the pre-set voltage is reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a capacitor-less linear regulator is used to eliminate external capacitors and reduce board cost, then device complexity and board area are reduced, but load stability and transient response deteriorate due to power-up overstress and voltage overshoot
Solution Approach 1:
The patent applies preliminary action by implementing a slew rate control circuit that is activated during power-up to preemptively control the voltage rise at the gate node before the output voltage can overshoot. The circuit includes a switch transistor and diode-connected transistor that form a current mirror to limit the charging current to the gate capacitor during startup, preventing the harmful voltage spike before it occurs. Once the output voltage reaches a predetermined level (detected by a level detection circuit), the slew rate control is automatically disabled.
Solution Approach 2:
The patent applies preliminary anti-action by introducing a circuit that produces an opposing effect to counteract the harmful voltage rise during power-up. The slew rate control circuit generates a controlled current that opposes the uncontrolled voltage spike at the gate node by limiting the charging rate through the diode-connected transistor and switch transistor configuration, thereby preventing output voltage overshoot before it can degrade load stability.
2Productivity
If the gate voltage rises quickly during power-up to reach operating voltage faster, then productivity is improved, but output voltage overshoot increases causing harmful overstress to load devices
Solution Approach 1:
The patent applies dynamics by making the slew rate control characteristic variable rather than fixed. The circuit dynamically adjusts the gate voltage charging rate based on the operating condition: during power-up, the switch transistor is ON providing a controlled slew rate to prevent overshoot; when the output voltage reaches the predetermined level, the level detection circuit turns OFF the switch transistor, disabling the slew rate control and allowing full-speed operation. This dynamic switching resolves the contradiction between fast startup and overshoot prevention.
Solution Approach 2:
The patent applies preliminary action by preparing the slew rate control circuit to activate automatically during the power-up phase before any harmful overshoot can occur. The circuit is designed to be inherently active during startup conditions and automatically disables itself when the output voltage reaches the safe operating level, eliminating the need for external control while preventing both overshoot and maintaining productivity.
Data Source
AI summary
An amplifier circuit includes an amplifier and an output transistor. The amplifier is coupled to an output node of the output transistor for providing an output voltage to a load device. The amplifier circuit also includes a slew-rate control circuit coupled to a gate node of the output transistor and configured to control voltage rise of the gate node of the output transistor during power-up to reduce output voltage overshoot.