CAPDAC Reset Switching in IMD ADCs for Accurate Low-Power Conversion

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Solution Overview

Problem

Implantable medical devices face challenges in minimizing power consumption for digital signal processing, particularly in analog-to-digital conversion, which affects the longevity of primary cell devices and the frequency of recharging in rechargeable devices.

Innovation Solution

The implementation of a capacitive digital-to-analog converter (CAPDAC) resetting technique in implantable medical devices, where the CAPDAC output is disconnected from the negative feedback input of a continuous time integrator and connected to a pseudo load during reset, allowing for accurate resetting with minimal impact on the integrator's feedback, and using a sample and hold capacitor to maintain the previous output value temporarily.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the CAPDAC is reset frequently to maintain accuracy, then the measurement precision is improved, but the power consumption increases

Engineering Contradiction:
ImproveCAPDAC output accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by performing the CAPDAC reset operation at predetermined intervals rather than continuously or on-demand. The microprocessor is configured to reset the CAPDAC output to a predetermined value at specific timing moments, which maintains measurement accuracy while avoiding unnecessary reset operations that would consume additional power. This periodic reset strategy balances precision requirements with power conservation in the implantable medical device.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If the reset duration is extended to ensure proper resetting, then the measurement precision is improved, but the productivity decreases

Engineering Contradiction:
Improvereset accuracyVSAvoidconversion speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent implements the skipping principle by executing the CAPDAC reset operation as a brief, focused action at predetermined intervals rather than as a prolonged continuous process. The microprocessor rapidly resets the CAPDAC output to the predetermined value and then immediately resumes normal conversion operations. This approach ensures proper resetting accuracy while minimizing the time spent in reset state, thereby maintaining high productivity and conversion speed in the analog-to-digital converter.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Measurement precision

If higher resolution analog-to-digital conversion is implemented, then the measurement precision is improved, but the use of energy increases

Engineering Contradiction:
Improveconversion resolutionVSAvoidcurrent drain
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by pre-setting the CAPDAC output to a predetermined value at specific intervals, which enables high-resolution conversion without requiring continuous high-power operations. This periodic preparation and reset mechanism allows the converter to maintain high measurement precision while consuming less energy compared to continuous high-resolution conversion modes, making it suitable for implantable medical devices with limited power resources.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7479910B1Capacitive digital-to-analog converter reset in an implantable medical device analog-to-digital converter
Publication Date: 2009.01.20 MEDTRONIC INC
  • US7479910B1 patent drawing
  • US7479910B1 patent drawing
  • US7479910B1 patent drawing

AI summary

In general, this disclosure describes techniques for capacitive digit-to-analog converter (CAPDAC) resetting in an implantable medical device (IMD) analog-to-digital converter (ADC). The CAPDAC of an IMD ADC may occasionally be reset to increase the accuracy of its output. The output of the CAPDAC may be disconnected from a negative feedback input of an integrator and connected to a pseudo load during the reset. Disconnecting the CAPDAC from the negative feedback input of the integrator reduces the affect of the reset on the integrator. During the reset of the CAPDAC, the negative feedback input of integrator is coupled to a sample and hold capacitor, which temporarily provides an input approximately equal to a previous, e.g., immediate, value of the output of CAPDAC prior to the reset. Thus, the resetting of the CAPDAC is done in such a manner that the affect of the reset on integrator is substantially reduced or eliminated.