Capless LDO Regulator With One-Shot Load Transient Control
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Solution Overview
Problem
Existing USB2.0 technology faces challenges in optimizing power efficiency and device reliability due to densely packed transistors, with conventional DC-to-DC converters and LDO regulators being inefficient, area-consuming, and unable to quickly track output load changes without causing noise or requiring external capacitors.
Innovation Solution
A capless low dropout (LDO) regulator using a one-shot circuit with pull-up/pull-down switches for fast output voltage adjustment during load changes, eliminating the need for external capacitors and feedback loops, and utilizing a bandgap reference voltage generator for stable output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a DC-to-DC converter is used to convert 1.8V to 1.2V, then voltage conversion is achieved, but power efficiency is poor and silicon area is increased
Solution Approach 1:
The patent changes the operating parameters of the LDO regulator by dynamically adjusting the reference voltage level based on the output load conditions. The reference voltage is changed from a fixed value to a variable value that adapts to load requirements, enabling the regulator to maintain optimal efficiency across different operating points while using minimal silicon area.
Solution Approach 2:
The patent introduces dynamic behavior to the LDO regulator by making the reference voltage adjustable in real-time based on load conditions. This dynamic adaptation allows the regulator to respond quickly to load changes without requiring large output capacitors, thereby reducing silicon area while maintaining power efficiency.
2Loss of energy
If an LDO regulator is used for voltage conversion, then power efficiency is improved, but it cannot track output load changes quickly and generates noise
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the reference voltage level in anticipation of load changes. The circuit detects load conditions and proactively modifies the reference voltage before the load change fully impacts the output, enabling faster tracking response without generating excessive noise or requiring large capacitors.
3Speed
If the LDO regulator is made fast to track load changes, then load tracking speed is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by making adjustments to the reference voltage only when and to the extent necessary to track load changes. Rather than continuously maximizing the response speed, the circuit makes minimal necessary adjustments to the reference voltage, achieving adequate load tracking speed while minimizing the power consumption penalty associated with fast response mechanisms.
4Speed
If a large capacitor is placed at the output node of the LDO, then load tracking performance is improved, but silicon area increases or external components are required
Solution Approach 1:
The patent extracts the need for large output capacitors by fundamentally changing how the LDO regulator responds to load changes. Instead of relying on capacitor energy storage to maintain output voltage during transient loads, the circuit uses dynamic reference voltage adjustment to proactively control the pass transistor, eliminating the requirement for large external or on-chip capacitors and thereby reducing silicon area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capless LDO regulator provides efficient, fast, and area-saving voltage conversion, supporting USB2.0 communication with improved power management and reduced silicon area requirements.
Implementation Method 1
the constant reference voltage is generated by a bandgap reference voltage generator
Data Source
Figure 1~2B
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AI summary
A circuit for converting a first voltage to a second voltage in a system is disclosed. The circuit includes a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage. The circuit is also includes an error amplifier. The error amplifier includes a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port. A second switch is included and is coupled between the first voltage and an output of the error amplifier. The output of the error amplifier is coupled with the gate of the pass transistor. A third switch is included and is coupled between ground and the output of the error amplifier. The second switch is configured to be driven by a first one shot pulse generated from an input signal of the system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.