Capless LNA ESD Clamp Layout for Lower Noise Figure
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Solution Overview
Problem
Conventional ESD clamps are inadequate for low-noise amplifiers (LNAs) lacking a DC blocking input capacitor, leading to degraded noise figure and insufficient ESD protection, particularly in ICs with multiple LNAs coupled to a common voltage source.
Innovation Solution
Implementing a distributed ESD clamp and protection circuit in each LNA, coupled between the voltage source terminal and a reference potential, using diodes and FETs to quickly shunt ESD current to ground, and incorporating a distributed ESD clamp to minimize routing distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ESD clamp is used in an LNA without a DC blocking input capacitor, then ESD protection is provided, but the noise figure is degraded due to diode leakage and voltage across diodes
Solution Approach 1:
The ESD protection function is segmented into two separate circuits: an ESD protection circuit (with diodes D1 and D2) and a distributed ESD clamp (with transistors Q1-Q4). This segmentation allows each circuit to be optimized for its specific function, with the protection circuit handling ESD events and the clamp minimizing noise figure degradation through selective activation based on voltage thresholds.
Solution Approach 2:
The ESD clamp circuit dynamically activates based on voltage conditions. The transistors Q1-Q4 are designed to conduct only when voltage exceeds certain thresholds (VDD + 0.6V or below VDD - 0.6V), allowing the circuit to remain inactive during normal operation and thus minimize noise figure impact while providing protection during ESD events.
2Device complexity
If multiple LNAs are coupled to a common voltage source, then circuit integration is improved, but ESD protection becomes insufficient without individual protection circuits
Solution Approach 1:
Each LNA is equipped with its own distributed ESD clamp circuit, segmenting the protection function to individual amplifiers. This ensures that an ESD event affecting one LNA does not impact others sharing the common voltage source, while maintaining overall system integration.
Solution Approach 2:
The ESD protection is implemented with local quality by placing the distributed clamp circuit locally at each LNA's voltage source terminal. This local implementation provides targeted protection where needed while allowing other LNAs to share the common voltage source without additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances ESD protection and improves noise figure by reducing diode leakage and voltage across diodes, resulting in a 0.1 dB average improvement across RF telecommunication bands.
Implementation Method 1
an ESD event applied to an IC input pad or pin may cause damage to FETs within the IC
Implementation Method 2
The ESD protection circuit includes a first diode having an anode coupled to the reference potential and a cathode coupled to the input terminal, and a second diode having an anode coupled to the input terminal and a cathode coupled to the voltage source terminal
Implementation Method 3
a distributed electro-static discharge clamp coupled between the reference potential and a node located between the electro-static discharge protection circuit and the voltage source terminal
Data Source
AI summary
Circuits and methods for providing ESD protection, particularly for LNAs lacking a DC blocking input capacitor (“capless LNAs”). Novel circuitry provides both improved ESD protection and an improved Noise Figure compared to conventional designs. One embodiment includes an integrated circuit including a voltage source pin and a plurality of low-noise amplifiers lacking a respective DC blocking input capacitor, each of the plurality of low-noise amplifiers including: a voltage source terminal coupled to the voltage source pin, an input terminal configured to receive a signal to be amplified, an output terminal configured to output an amplified version of the received signal to be amplified, an ESD protection circuit coupled to the input terminal and to both the voltage source terminal and a reference potential, and a distributed ESD clamp coupled between the reference potential and a node located between the ESD protection circuit and the voltage source terminal.