Capped Air-Gap Spacer Structure for Low-Capacitance Gate Isolation

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Solution Overview

Problem

As semiconductor devices evolve to higher integration densities and finer dimensions, they face challenges in achieving improved electrical properties and reducing parasitic capacitance to enhance operation speed and efficiency.

Innovation Solution

The semiconductor device incorporates a gate structure with a unique spacer configuration, including a first spacer, an air-gap spacer, and a second spacer, where the second spacer is bent to cap the air-gap spacer, along with distinct insulating layers and a gate capping layer, to improve electrical insulation and reduce parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If integration density is increased to achieve higher performance, then device functionality is improved, but parasitic capacitance increases which reduces operation speed

Engineering Contradiction:
Improveintegration densityVSAvoidoperation speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent extracts the harmful capacitive coupling between adjacent gate electrodes by introducing air-gap spacers that create physical separation. The air-gap spacer removes the dielectric material between gates, eliminating the parasitic capacitance pathway while maintaining close spacing for high density.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The air-gap spacer acts as an intermediary structure between adjacent gate electrodes. It provides physical separation and electrical isolation, mediating the interaction between neighboring gates to prevent capacitive coupling while allowing the gates to remain in close proximity for high integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If air-gap spacer is introduced to reduce parasitic capacitance, then operation speed is improved, but structural stability deteriorates

Engineering Contradiction:
Improveoperation speedVSAvoidstructural stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The spacer structure is segmented into multiple components: a first spacer providing initial separation, an air-gap spacer providing capacitive isolation, and a second spacer providing additional structural support. This segmentation allows each component to fulfill specific functions while collectively maintaining stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The spacer system uses composite structure combining different materials with distinct properties. The air-gap region provides electrical isolation, while the surrounding dielectric spacers provide mechanical support. This composite approach balances electrical performance with structural stability.

Inventive Principle:
Principle #40Composite materials

3Stability of the object's composition

If multiple spacer layers are added to stabilize air-gap spacer, then structural stability is improved, but device complexity increases

Engineering Contradiction:
Improvestructural stabilityVSAvoiddevice complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The first spacer, air-gap spacer, and second spacer are formed as an integrated multi-layer structure through sequential deposition processes. This merging of functions into a unified spacer system provides stability while maintaining manufacturing efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The first spacer is formed preliminarily before the air-gap spacer to establish the initial structural framework. This preliminary action creates a stable base that simplifies subsequent formation of the air-gap region and second spacer, reducing overall process complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12191373B2Method of forming a semiconductor device with capped air-gap spacer
Publication Date: 2025.01.07 SAMSUNG ELECTRONICS CO LTD
  • US12191373B2 patent drawing
  • US12191373B2 patent drawing
  • US12191373B2 patent drawing

AI summary

A method includes: forming a sacrificial gate structure on the active region; forming a spacer structure including a first spacer, a second spacer, and an air-gap spacer, the air-gap spacer capped by bending an upper portion of the second spacer toward an upper portion of the first spacer; forming an insulating structure on the sides of the spacer structure; forming a gap region; and forming a gate structure including a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region. The upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface, and a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level.