Interconnect Airgaps with Capped Cavities for Capacitance Reduction
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Solution Overview
Problem
The existing interconnect structures in semiconductor fabrication, particularly in the back-end-of-line (BEOL) portion, face challenges with capacitance reduction due to damage from etching processes that erode and bevel metal corners, increasing resistance and reducing the effectiveness of airgaps in low-k dielectric materials.
Innovation Solution
A method involving selective deposition of dielectric layers on interconnects and the interlayer dielectric layer, followed by controlled etching to form cavities with capped airgaps, where the dielectric layers prevent corner erosion and ensure minimal dielectric coverage on sidewalls, thereby maintaining low capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If an etching process is used to remove the interlayer dielectric layer and define cavities for airgaps, then capacitance is reduced, but the etching process damages the metal lines by eroding and beveling corners, increasing resistance
Solution Approach 1:
A conformal dielectric layer is deposited over the metal lines and interlayer dielectric before etching. This preliminary protective layer prevents the etching process from directly contacting and damaging the metal lines, thus maintaining corner sharpness and reducing resistance while still allowing airgap formation for capacitance reduction
Solution Approach 2:
The conformal dielectric layer acts as an intermediary between the etching process and the metal lines. It allows the etching to proceed for airgap formation while mediating the harmful effects on the metal, protecting the lines from erosion and beveling
2Reliability
If a conformal dielectric layer is deposited to encapsulate airgaps, then airgaps are protected, but the dielectric layer forms on sidewalls of lines, reducing capacitance reduction benefits
Solution Approach 1:
The conformal dielectric layer is applied with varying thickness or presence in different locations. It is thinner or absent on sidewalls where capacitance reduction is critical, while providing sufficient coverage for airgap encapsulation in other areas, thus balancing protection with capacitance optimization
Solution Approach 2:
The conformal dielectric layer is applied partially rather than uniformly across all surfaces. It provides just enough coverage to protect and encapsulate airgaps while deliberately limiting deposition on sidewalls to minimize the capacitance penalty, using partial action to achieve the optimal balance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance by preventing metal corner erosion and optimizing airgap formation, leading to improved performance and reduced resistance in interconnects.
Implementation Method 1
An etching process is used to remove the interlayer dielectric layer between the lines and define cavities in regions where airgaps are desired
Implementation Method 2
A conformal dielectric layer is deposited that coats the surfaces surrounding the cavities and pinches off at the cavity entrances to surround and encapsulate the airgaps
Implementation Method 3
airgaps, which have a minimum achievable permittivity
Data Source
AI summary
Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level has a first interconnect, a second interconnect, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first interconnect adjacent to the entrance of the cavity and a second section arranged on the second interconnect adjacent to the entrance of the cavity. A second dielectric layer is formed on the first section of the first dielectric layer and the second section of the first dielectric layer. The second dielectric layer extends from the first section of the first dielectric layer to the second section of the first dielectric layer and across the entrance to the cavity to close an airgap between the first interconnect and the second interconnect.