Capping Layer Structure for Isolation in FinFET Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In down-scaled semiconductor devices, maintaining isolation margins while reducing the interval between interconnection layers and contact plugs is a challenge, particularly in integrated circuit devices with field effect transistors, where precise spacing and material composition are critical to prevent short circuits and ensure effective etching resistance.
Innovation Solution
The integrated circuit device incorporates a complex capping layer structure with different compositions for the gate lines and insulating spacers, including a bottom capping layer, core capping layer, and sidewall capping layer, which extends parallel to the gate lines and overlaps the insulating spacer, providing enhanced etch resistance and isolation between conductive plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the interval between interconnection layer and contact plug is reduced to down-scale the device, then device size decreases, but isolation margin is compromised
Solution Approach 1:
The capping layer extends in the lateral direction beyond the gate line to overlap the insulating spacer, utilizing the horizontal dimension to provide etch resistance and isolation protection without increasing vertical device height. This lateral extension allows compact vertical stacking while maintaining isolation margins through horizontal material coverage.
Solution Approach 2:
The capping layer comprises multiple materials with different compositions (e.g., first material and second material with different etch selectivities) to provide differentiated functions: one material provides etch resistance during contact hole formation while another material provides isolation protection. This composite structure enables simultaneous achievement of small device footprint and reliable isolation margins.
2Reliability
If complex capping layer structure with different compositions is used, then etch resistance and isolation are improved, but device complexity increases
Solution Approach 1:
Different materials within the capping layer are positioned at specific locations: the first material is placed where etch resistance is needed (overlapping the gate line), while the second material is placed where isolation is needed (overlapping the insulating spacer). This local differentiation provides targeted functionality without requiring a completely complex multi-layer structure throughout the entire device.
Solution Approach 2:
The capping layer structure serves multiple functions simultaneously: it provides etch resistance during contact hole formation, maintains isolation margins between conductive plugs, and enables lateral extension to overlap the insulating spacer. By designing a single capping layer system that performs these multiple functions, the patent avoids the need for separate dedicated structures for each function, thereby managing complexity.
Data Source
AI summary
An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.