Capping Mask Layout for Parasitic Active Region Prevention
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Solution Overview
Problem
The formation of parasitic active regions due to parasitic mask patterns in the interface regions or peripheral circuit regions of semiconductor devices, which occur as feature sizes decrease, leading to issues during the patterning process.
Innovation Solution
A mask structure is provided that includes a capping mask layer and etch patterns to form trenches without a separate trimming process, reducing or preventing the formation of parasitic active regions by using a capping mask line that covers the interface and peripheral circuit regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are reduced to achieve high integration, then device integration density is improved, but parasitic mask patterns are formed in interface regions causing defective active regions
Solution Approach 1:
The substrate is divided into three distinct regions: a first region with high active region density, a second region with low active region density, and an adjacent interface region between them. This segmentation allows different mask patterns to be applied to different regions, preventing parasitic mask formation in the interface region while maintaining high integration in the cell array region.
Solution Approach 2:
Different mask patterns are applied to different regions of the substrate. The first mask pattern is formed in the first region, the second mask pattern is formed in the second region, and the capping mask line is formed in the adjacent region. This local differentiation ensures that each region receives the appropriate mask coverage to prevent parasitic active regions while maintaining the desired active region density.
2Ease of manufacture
If conventional mask patterns are used in interface regions, then patterning process is simplified, but parasitic active regions are formed requiring additional trimming processes
Solution Approach 1:
A capping mask line is formed in advance in the adjacent region before the main patterning process. This preliminary action prevents parasitic mask patterns from forming in the interface region during subsequent etching processes, eliminating the need for additional trimming steps to remove defective active regions.
Solution Approach 2:
The capping mask line acts as an intermediary element between the first mask pattern and the second mask pattern in the adjacent region. It controls the etching process to prevent parasitic mask formation without interfering with the formation of active regions in the first and second regions.
3Productivity
If minimum margin horizontal widths are used in interface regions, then device integration is improved, but parasitic mask patterns cannot be prevented during patterning
Solution Approach 1:
The mask pattern structure is locally optimized for the adjacent region by introducing a capping mask line that specifically addresses the parasitic mask problem in interface regions, while maintaining minimum margin horizontal widths to achieve high device integration.
Solution Approach 2:
The capping mask line is positioned to preemptively block the formation of parasitic mask patterns in the adjacent region during the patterning process, counteracting the harmful effect before it can occur.
Data Source
AI summary
Provided is a method of manufacturing a semiconductor device, the method including: forming a mask stack, wherein the substrate includes a first region and a second region with different active region densities and an adjacent region between the first region and the second region; forming, on the capping mask layer, a first etch pattern that does not cover the first region and is on the second region and the adjacent region; forming a capping mask line by removing a portion of the capping mask layer by using the first etch pattern as an etch mask; forming a second etch pattern on the capping mask; and forming a mask pattern by removing a portion of the mask stack by using the capping mask line and the second etch pattern as etch masks.