Programmable Capture Clock Generation for Scan Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit testing methods require manual adjustment of clock circuitry for each test pattern, leading to inefficiencies in scan testing due to varying numbers of at-speed clock pulses needed, which complicates the capture of test results.
Innovation Solution
The implementation of programmable clock control mechanisms within microcircuit designs that generate the required number and location of at-speed capture clocks during scan tests, utilizing capture clock generation circuits and control registers like JTAG or scan registers to configure clock pulses based on stored control data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual adjustment of clock circuitry is used for each test pattern, then flexibility in handling different test patterns is achieved, but testing efficiency and productivity deteriorate due to repetitive manual adjustments
Solution Approach 1:
The capture clock generation circuit is configured to automatically generate the required number of at-speed capture clocks based on control data stored in registers, eliminating the need for manual adjustment of clock circuitry for each test pattern. The system self-adjusts according to the test pattern requirements without human intervention.
Solution Approach 2:
Control data specifying the number and location of at-speed capture clocks is pre-stored in registers before testing begins. This preliminary configuration allows the capture clock generation circuit to automatically generate the correct number of clock pulses for each test pattern without requiring manual adjustment during the testing process.
2Reliability
If the number of at-speed clock pulses is varied for different test patterns, then comprehensive test coverage is achieved, but device complexity increases due to the need for manual clock circuitry adjustment
Solution Approach 1:
The capture clock generation circuit automatically determines and generates the required number of at-speed capture clocks based on control data, eliminating the need for manual adjustment of clock circuitry. This maintains comprehensive test coverage while reducing operational complexity.
Solution Approach 2:
Registers store control data that serves as an intermediary between the test pattern requirements and the capture clock generation circuit. This intermediary mechanism translates varying test pattern requirements into automated clock pulse generation without requiring manual intervention in the clock circuitry.
3Productivity
If automated capture clock generation is implemented, then testing productivity is improved, but initial device complexity increases due to addition of control circuitry
Solution Approach 1:
The capture clock generation circuit is designed to handle multiple test patterns with different numbers of required capture clocks through a single unified circuit. The same circuit generates at-speed capture clocks for various test scenarios by simply changing the control data in registers, eliminating the need for multiple specialized clock generation circuits.
Solution Approach 2:
Instead of adding complex hardware for each test pattern, the system changes operational parameters (number and location of at-speed capture clocks) by modifying control data in registers. This parameter-based configuration allows a single capture clock generation circuit to adapt to different test requirements without increasing hardware complexity.
Data Source
AI summary
A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.