Selective Carbon-Doped Epitaxial Cap Layer for PMOS Strain Engineering
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Solution Overview
Problem
Current methods for forming epitaxial SiGe in PMOS transistors do not effectively enhance carrier mobility and mechanical stress across the channel region, limiting the performance of PMOS transistors.
Innovation Solution
The formation of epitaxial SiGe regions using a selective recessed strained source/drain process, combined with a carbon-doped epitaxial cap layer, is employed to induce compressive strain and improve hole mobility, involving techniques like reduced-temperature chemical vapor deposition (RTCVD) and subsequent silicidation with a nickel-based silicide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial SiGe formation methods are used, then the manufacturing process is simple, but carrier mobility and mechanical stress across the channel region are not effectively enhanced
Solution Approach 1:
The epitaxial formation process is segmented into two distinct stages: first forming the SiGe layer, then forming a separate cap layer on top. This segmentation allows each layer to be optimized independently - the SiGe layer provides the necessary mechanical stress while the cap layer protects against Ge precipitation, thereby enhancing carrier mobility without overly complicating the overall process.
Solution Approach 2:
The SiGe layer is formed preliminarily before the cap layer, establishing the mechanical stress foundation early in the process. This preliminary action of creating the strained SiGe layer first enables subsequent optimization of the cap layer to protect the Ge atoms without compromising the already-established stress field that enhances carrier mobility.
2Stability of the object's composition
If a carbon-doped epitaxial cap layer is formed on selective epitaxial SiGe, then thermal stability of the silicide layer is improved, but the manufacturing process complexity increases
Solution Approach 1:
The carbon-doped epitaxial cap layer serves as an intermediary protective barrier between the Ge atoms in the SiGe layer and the high-temperature processing environment. This intermediate cap layer prevents Ge precipitation during subsequent thermal processing and silicidation steps, thereby improving thermal stability while the carbon doping enhances the protective capability of this intermediate layer.
Solution Approach 2:
The cap layer is formed as a composite material combining silicon, carbon, and dopants (such as boron). This composite structure provides superior thermal stability compared to pure silicon, as the carbon content prevents Ge precipitation and the dopants adjust the electrical and mechanical properties. The composite nature of this cap layer enables it to withstand high-temperature processing while protecting the underlying SiGe structure.
3Reliability
If selective recessed strained source/drain process is used, then hole mobility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The selective recessed strained source/drain process applies different material compositions and structures to different locations: SiGe is deposited only in the source/drain regions where strain is needed to enhance hole mobility, while the channel region maintains its original structure. This local quality approach ensures that the strain-enhanced mobility benefit is applied precisely where needed without affecting other regions, thereby improving manufacturing precision in the strain engineering process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases PMOS transistor drive current by enhancing carrier mobility and thermal stability of the silicide layer, leading to improved transistor performance.
Implementation Method 1
The selective C-doped epi cap layer 270 facilitates the thermal stability of the subsequently formed silicide layer 160 (by inhibiting Ge precipitation and film agglomeration during the silicidation process)
Implementation Method 2
reduced-temperature chemical vapor deposition (RTCVD)
Implementation Method 3
subsequent silicidation with a nickel-based silicide layer
Data Source
AI summary
A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.