Carbon-Doped Offset Spacers for Semiconductor Stress Layer Integrity
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Solution Overview
Problem
Semiconductor devices with embedded SiGe and SiC technologies face issues such as unacceptable electrical properties due to the formation of defective stress layers on the side surfaces of gate structures during the fabrication process, which can deteriorate the stability and reliability of the devices.
Innovation Solution
The method involves doping offset spacers with carbon ions to enhance their anti-corrosion ability, preventing exposure of the side surfaces during etching processes and subsequent stress layer formation, thereby preventing the formation of defective layers and improving the stability and reliability of the semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If offset spacers are formed without stability doping, then the fabrication process is simpler and faster, but the etching rate of spacers is too high causing exposure of side surfaces and formation of defective stress layers
Solution Approach 1:
The offset spacers are doped with carbon ions before the etching process to pre-establish their anti-corrosion ability. This preliminary doping action ensures that when subsequent etching and stress layer formation occur, the spacers maintain their structural integrity and prevent exposure of the gate structure side surfaces, thereby avoiding defective layer formation.
Solution Approach 2:
The carbon ion doping process changes the chemical composition and physical properties of the offset spacer material. By introducing carbon atoms into the spacer structure, the etching rate parameter is modified to become sufficiently low, providing the required anti-corrosion ability while maintaining process feasibility.
2Reliability
If embedded SiGe or SiC technology is used to apply stress, then carrier mobility is improved, but defective layers form on gate structure side surfaces deteriorating device reliability
Solution Approach 1:
The carbon-doped offset spacers serve as a protective barrier that prevents the formation of defective layers on the gate structure side surfaces. By establishing this protective layer beforehand, the harmful effect of defective stress layer formation is counteracted, allowing the beneficial stress effects on carrier mobility to be realized without the detrimental side effects.
Solution Approach 2:
The carbon-doped offset spacers act as an intermediary protective structure between the etching/stress layer formation process and the gate structure. This intermediary layer absorbs the harmful effects of the fabrication process, preventing direct damage to the gate structure while still allowing the desired stress to be applied to the channel region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces the etching rate of the spacers and prevents the exposure of side surfaces, leading to improved electrical properties and reliability of the semiconductor devices by maintaining the integrity of the stress layers and gate structures.
Implementation Method 1
doping offset spacers with carbon ions to enhance their anti-corrosion ability
Implementation Method 2
The lattice mismatch between the silicon substrate and the SiGe material can generate a compressive stress to the channel region; the performance of the PMOS device can be improved. Similarly, the embedded SiC technology is often used to apply a tensile stress to the channel region of an NMOS device
Data Source
AI summary
A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches.