Carbon-Doped Semiconductor Layers for Boron Phosphorus Diffusion Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor memory devices face challenges in preventing the diffusion of boron and phosphorus dopants during high-temperature manufacturing processes, which can lead to deviations in threshold voltages and reduced transistor performance due to mutual diffusion through tungsten silicide in gate electrodes.
Innovation Solution
The semiconductor memory device incorporates semiconductor layers containing carbon to prevent boron and phosphorus diffusion, with a thin insulating layer to further suppress their penetration into conductive layers and the substrate, maintaining transistor characteristics and facilitating manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-temperature manufacturing processes are used, then manufacturing productivity is improved, but dopant diffusion increases causing threshold voltage deviation
Solution Approach 1:
A carbon-containing semiconductor layer is introduced as an intermediary barrier between the dopant source and the tungsten silicide gate electrode. This intermediate layer prevents direct diffusion of boron and phosphorus into the gate electrode during high-temperature manufacturing processes, thereby maintaining threshold voltage precision while allowing high-productivity manufacturing to proceed.
Solution Approach 2:
The gate electrode structure is transformed from a simple tungsten silicide layer to a composite structure comprising multiple layers: the tungsten silicide gate electrode, an intermediate carbon-containing semiconductor layer, and an upper semiconductor layer. This composite structure provides diffusion barrier functionality while maintaining electrical characteristics, resolving the contradiction between high-temperature processing capability and dopant diffusion prevention.
2Device complexity
If conventional gate electrode structure is used, then device complexity is reduced, but dopant diffusion through tungsten silicide occurs
Solution Approach 1:
The gate electrode structure is segmented into distinct functional layers: the tungsten silicide gate electrode layer, an intermediate carbon-containing semiconductor layer serving as a diffusion barrier, and an upper semiconductor layer. This segmentation allows each layer to perform its specific function while maintaining overall structural simplicity and manufacturing feasibility.
3Manufacturing precision
If carbon-doped semiconductor layers are added, then dopant diffusion is suppressed, but manufacturing process complexity increases
Solution Approach 1:
The carbon-containing semiconductor layer is formed by combining carbon doping with existing semiconductor layer formation processes. The carbon is introduced during standard semiconductor manufacturing steps, merging the diffusion barrier functionality with the existing process flow rather than adding entirely separate manufacturing steps, thereby limiting the increase in process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the diffusion of boron and phosphorus, maintaining desired transistor performance and simplifying the manufacturing process by using carbon-doped semiconductor layers and a thin insulating layer to prevent dopant penetration.
Implementation Method 1
prevent the diffusion of boron and phosphorus dopants during high-temperature manufacturing processes
Implementation Method 2
semiconductor layers containing carbon to prevent boron and phosphorus diffusion
Data Source
AI summary
A semiconductor memory device includes a P-type transistor and a first N-type transistor. The P-type transistor includes a first semiconductor layer containing carbon, a P-type second semiconductor layer provided on the first semiconductor layer, a third semiconductor layer provided on the second semiconductor layer and containing carbon. The first N-type transistor includes a fourth semiconductor layer containing carbon, an N-type fifth semiconductor layer provided on the fourth semiconductor layer, a sixth semiconductor layer provided on the fifth semiconductor layer and containing carbon.