Carbon-Doped Source Contact Layer for 3D Memory Boron Diffusion Control
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in maintaining the integrity of semiconductor channels due to boron diffusion from source contact layers, which affects the reliability and performance of memory devices.
Innovation Solution
The implementation of a carbon-doped source contact layer in combination with boron-doped semiconductor materials, where the upper semiconductor layer is doped with carbon to reduce boron diffusion into the semiconductor channels, and the source contact layer is formed using a third boron-doped material, along with an alternating stack of insulating and conductive layers, to create memory stack structures that vertically extend through the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a source contact layer is formed using boron-doped semiconductor material, then the electrical conductivity of the source contact layer is improved, but boron diffusion into the semiconductor channels occurs, degrading channel integrity and device reliability
Solution Approach 1:
An intermediate layer is introduced between the boron-doped source contact layer and the semiconductor channel. This intermediate layer acts as a diffusion barrier that prevents boron atoms from migrating into the channel region, thereby eliminating the harmful diffusion effect while preserving the electrical conductivity function of the source contact layer
Solution Approach 2:
The problematic boron doping is extracted or removed from the source contact layer configuration. Instead of using boron-doped material directly in contact with the channel, the patent employs alternative doping strategies or material compositions for the source contact layer that maintain conductivity without introducing boron diffusion risks
2Reliability
If the source contact layer is heavily doped to improve conductivity, then the electrical performance is enhanced, but the diffusion of dopant atoms into adjacent regions increases, affecting manufacturing precision
Solution Approach 1:
The patent applies different doping concentrations and types to different regions of the source contact layer structure. The region adjacent to the channel uses lower doping or different dopant species to minimize diffusion, while other regions maintain higher doping for optimal conductivity, creating a spatially varying doping profile that balances electrical performance with precision control
3Device complexity
If conventional source contact layer structures are used, then the device structure is simpler, but semiconductor channel integrity is compromised due to dopant diffusion
Solution Approach 1:
An intermediate barrier layer is inserted between the source contact layer and the semiconductor channel. This additional layer serves as a diffusion barrier that protects channel integrity while the overall structure remains relatively simple and compatible with existing manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces boron diffusion, enhancing the reliability and performance of three-dimensional memory devices by maintaining the integrity of semiconductor channels and improving the overall memory stack structure.
Implementation Method 1
the upper semiconductor layer comprises a carbon doped second boron-doped semiconductor material
Data Source
AI summary
A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer. Carbon atoms in the upper semiconductor layer and optionally the lower semiconductor layer suppress diffusion of boron atoms into the vertical semiconductor channel.


